As process geometries continue to shrink to the 45nm node and beyond, the resulting increases in design complexity and
chip pattern density have fueled a data explosion on advanced semiconductor designs. This extends product
development cycles and potentially impacts product yield.
Two areas in the design flow that are most adversely affected include both mask synthesis (OPC, RET) and Mask Data
Preparation. Minimizing data I/O and providing an integrated optical proximity correction (OPC) and mask data
preparation solution (MDP), plays an increasingly critical role in reducing the mask synthesis and mask data prep total
cycle time.
In this paper, an integrated flow of Proteus OPC and CATS MDP are discussed. This integrated flow virtually eliminates
the data I/O step between OPC and MDP pre-processing and delivers faster total turn around time by effectively
eliminating the time originally spent on MDP pre-processing. The integrated flow and its turn around time performance
will be presented.
In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as
phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.
At the deep Subwavelength process nodes, the use of the aggressive optical proximity correction (OPC) and resolution enhancement techniques (RET) is fostering an exponential increase in output database size causing the CPU time required for mask tape-out to increase significantly. This sets up challenging scenarios for integrated device manufacturers (IDMs), and Foundries. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround for a CMOS process around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes. Unlike silicon processing, masks tape-out time can be decreased by applying a combination of extra computing resources and enhancements in the OPC tool like Fracture Friendly OPC (FFOPC) . Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue. Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl's law. Very few are efficient enough to allow the effective use of 100's of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.
For the manufacturing of 65nm technology devices, many exposure techniques that have been used in previous technology nodes cannot offer enough process window anymore. Alternating Aperture Phase Shift Mask (Alt-PSM) is one of the few remaining technologies that still offer enough resolution to enable 65nm production.
While setting up a 65nm Alt-PSM based resolution enhancement technique (RET) flow many of the mask manufacturability challenges need to be considered and addressed. At the same time OPC complexity is one of the main factors for increased data volume and high mask costs. In this work, logic and embedded memory cells are designed, and based on the specific geometries a manufacturable RET flow is developed. Data complexity reduction and lower mask cost are the primary motives in setting up this RET flow.
With the exponential increase in output database size due to the aggressive optical proximity correction (OPC) and resolution enhancement technique (RET) required for deep sub-wavelength process nodes, the CPU time required for mask tape-out continues to increase significantly. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround of a mature, plain-vanilla CMOS process of around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes.
Unlike silicon processing, masks tape-out time can be decreased by simply purchasing extra computing resources and software licenses. Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue.
Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl’s law. Very few are efficient enough to allow the effective use of 1000’s of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.
Resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential components in the sub-90nm silicon manufacturing process. For the 65nm generation, alternating phase shift masks (Alt-PSM) is recognized as a proven wafer imaging technique. The large process window and hence stable process control is one of the key properties which make it the most viable approach for 65nm production compared with other RET approaches.
On the mask making side, the good mask error enhancement factor (MEEF) performance of the Alt-PSM is a big plus as it makes the wafer CD control less susceptible for CD errors on the mask. Even though the benefits of Alt-PSM are well known, the reticle cost and manufacturing challenges have impeded its extensive adoption. In this work, we explore a methodology to reduce the Alt-PSM mask write time vis-a-vis cost, through certain data optimization techniques.
At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority.
Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.
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