Inverse lithography technology (ILT) and Curvilinear masks (CL masks) are playing a critical role in addressing the challenges of EUV as we move toward advanced nodes. However, CL masks may have shapes that are more challenging to Mask Rule Check (MRC) clean-up and mask manufacturing, like sharp angles, T/Y junctions, sharp turns, and too-small features. Running a CLMRC checks before mask making is a general practice that allows to quickly screen the full chip and identify potential mask problems before mask inspection. Last year, we presented one of the CLILT solutions to address the MRC challenges on the CLILT masks [1,2 and 3]. In this paper, we present a comprehensive study of the curvilinear Mask Rule Check (CL MRC) quality and runtime. We compare and discuss different CL MRC check and quality of the results. We will describe how to properly filter measurements to flag true MRC violations while excluding false violations. Finally, we demonstrate a flow to achieve significant runtime improvement on a full chip database.
Instead of using the inverse lithography technology (ILT) flow that allows for unrestricted shapes and widths of sub-resolution assist features (SRAFs), Y. Xu et al. propose an alternative approach. This method involves the direct specification of width, curvature, and minimal area to generate constant width curvilinear SRAFs. The study described in Ref. 1 demonstrates several advantages associated with constant width curvilinear SRAFs compared to their freeform counterparts. The advantages include improved compliance with manufacturing rule check (MRC) requirements, mitigation of SRAF printing issues, compatibility with the tile boundary stitching, enhanced runtime robustness, and better control over data volume. In the field of mask process correction (MPC), it is worth examining the potential advantages offered by constant width curvilinear SRAFs. Since all SRAFs must be printed on the mask but not on the wafer during the manufacturing process, the goal of MPC is the same for main features and SRAFs, aiming to ensure that patterns on the fabricated masks align precisely with target shapes and minimize edge placement errors (EPEs). This paper presents a comprehensive study of MPC accuracy and runtime performance when employing constant width SRAFs as input. A comparative analysis is conducted against the use of freeform SRAFs. Various MPC approaches, such as shape-based and dose-based corrections, treating SRAFs as a visible layer without edge bias, curvature-based prebias (CBB), and curvature-based fragmentation (CBF) are explored. The findings of this study provide valuable guidance for the generation of masks with constant width curvilinear SRAFs.
SRAF plays a critical role in mask synthesis. It is a fundamental component of masks, for Manhattan or curvilinear masks, and for DUV or EUV masks. ILT is one of the technologies that can produce high-quality curvilinear, modelbased SRAF. With this technology, the actual shapes of curvilinear assist features are naturally obtained by thresholding an optimized ILT mask that is represented as an image grid, ending up with freeform shapes. In this case, the ILT mask is formed through iterations of an optimization process. The shapes and widths of the freeform SRAF vary from location to location. Such SRAF is expected to deliver a wafer performance close to the optimum defined by the objective function. Nevertheless, the ILT-based curvilinear SRAF is an emerging technology, still on its way to full adoption in production. Therefore, this report focuses on the ILT SRAF obtained differently - constant width SRAF. Constant width SRAF is a more suitable starting point in addressing many practical concerns such as MRC compliance, SRAF printing avoidance, tile boundary stitching friendliness, run-time robustness, and data volume control. The SRAF in this study is characterized by skeletons, each of which is in turn given by the coordinates of ordered “critical” points. These critical points mainly consist of local minima of the gradient map of the objective function. Here the gradient map, roughly speaking, is the partial derivative of the ILT objective function with respect to the transmission values of a grid-represented mask. We will show that the shapes of such constant width SRAF closely match that of the freeform SRAF obtained by thresholding the iterated ILT mask, up to their locations and connectivity, and maintaining the EPE convergence and simulated wafer performance compatible with its freeform counterpart.
In the last decade, Photonics Technology has been an emerging technology for optical telecommunications and for optical interconnects in microelectronics. As a result, a large diversity of Photonics design methodologies has merged with very challenging scales and shapes. Manufacturing such curvy and critical photonics shapes requires advanced Resolution Enhancement Techniques (RET) including Inverse Lithography Techniques (ILT) with 193nm immersion lithography. In this paper, we investigate the manufacturing challenges of several Photonics devices using advanced ILT solutions and the SRAF insertion impact on delivering good litho quality including EPE, PVband and LER. We will demonstrate how our Calibre ILT solutions enable the manufacturing of the most challenging Photonics designs.
Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit
(PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides
functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is
why printing fidelity is very challenging on photonics patterns.
In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The
first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The
first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool
design and does not need any retargeting step before OPC. We will compare these two flows on various Si-
Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe
that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow
also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also
discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process
window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an
industrial environment.
The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing.
In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.
To print sub 22nm node features, current lithography technology faces some tool limitations. One
possible solution to overcome these problems is to use the double patterning technique (DPT). The
principle of the double patterning technique is pitch splitting where two adjacent features must be
assigned opposite masks (colors) corresponding to different exposures if their pitch is less than a
predefined minimum coloring pitch. However, certain design orientations for which pattern features
separated by more than the minimum coloring pitch cannot be imaged with either of the two exposures.
In these directions, the contrast and the process window are degraded because constructive
interferences between diffractive orders in the pupil plane are not sufficient. The 22nm and 16nm nodes
require the use of very coherent sources that will be generated using SMO (source mask cooptimization).
Such pixelized sources while helpful in improving the contrast for selected
configurations, can lead to degrade it for configurations which have not been counted for during the
SMO process. Therefore, we analyze the diffractive orders interactions in the pupil plane in order to
detect these limited orientations in the design and thus propose a new double patterning decomposition
algorithm to enlarge the process window and the contrast of each mask.
The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the
art scanner will be limited to a numerical aperture of 1.35. Thus we cannot "simply" apply a shrink factor from
the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions
in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to
enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is
clearly established that early process for these layers will be performed by double patterning technique coupled
with advanced OPC solutions.
In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS)
and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC
solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure
good process control.
This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored
by the French government.
In double patterning technology (DPT), two adjacent features must be assigned opposite colors,
corresponding to different exposures if their pitch is less than a predefined minimum coloring pitch.
However, certain design orientations for which pattern features separated by more than the minimum
coloring pitch cannot be imaged with either of the two exposures. In such cases, there are no aerial
images formed because in these directions there are no constructive interferences between diffractive
orders in the pupil plane. The 22nm and 16nm nodes require the use of pixelized sources that will be
generated using SMO (source mask co-optimization). Such pixelized sources while helpful in
improving the contrast for selected configurations can lead to degraded contrast for configurations
which have not been set during the SMO process. Therefore, we analyze the diffractive orders
interactions in the pupil plane in order to detect limited orientations in the design and thus propose a
decomposition to overcome the problem.
Double patterning (DP) is one of the main options to print devices with half pitch less than 45nm. The basis of DP is to
decompose a design into two masks. In this work we focus on the decomposition of the contact pattern layer. Contacts
with pitch less than a split pitch are assigned to opposite masks corresponding to different exposures. However, there
exist contact pattern configurations for which features can not be assigned to opposite masks. Such contacts are flagged
as color conflicts. With the help of design of manufacturing (DFM), the contact conflicts can be reduced through
redesign. However, even the state of the art DFM redesign solution will be limited by area constraints and will introduce
delays to the design flow. In this paper, we propose an optical method for contact conflicts treatment. We study the
impact of the split on imaging by comparing inverse lithography technology (ILT), optical proximity correction (OPC)
and source mask co-optimization (SMO) techniques. The ability of these methods to solve some split contacts conflicts
in double patterning are presented.
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