Mr. Pavel Izikson Profile

Pavel Izikson

Application Engineer

Area of Expertise:

metrology , lithography , overlay , data analysis

Publications (26)

Proceedings Article | 13 June 2022 Poster

Poster

Use of optical AEI metrology to compute overlay and etch-induced tilt in logic

Song Bai, Qingwei Liu, Xiaosong Yang, Yuntao Jiang, Gaoying Zhang, Yunhang Qiu, Alok Verma, Bert Verstraeten, Chaoyu Chen, Dennis Loeffen, Elton Bitinka, Giulia Argento, Martijn Jongen, Pavel Izikson, Huanian You, Perry Bao, Yvon Chai, Zhi-Yi Gao

Proceedings Volume 12053, 120531F (2022) https://doi.org/10.1117/12.2615979

KEYWORDS: Signal detection, Overlay metrology, Metrology, Logic, Scanning electron microscopy, Etching, Yield improvement, Optical metrology, Inspection, Front end of line

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In advanced logic nodes, edge placement error (EPE) budget becomes tighter. Such budget needs to account for items that were nearly negligible before FinFET era, such as rule-based etch bias error or overlay metrology to device (MTD) bias. Some of the new challenges are overlay metrology error due to process induced mark asymmetry, after Etch Inspection (AEI) pattern shift and aberration induced overlay difference between mark and device, all summarized as Metrology to Device bias. YieldStar In-Device Metrology (YS IDM) addresses device-like metrology and real AEI overlay, but in principle might suffer from process asymmetry. In this work we measure ASML Self Reference (ASR) targets by IDM. We use the detected IDM signal to quantify and address for the first time the asymmetry of the printed marks containing device-like structures on FEOL with respect to reference tool. Two main findings characterize this work: - IDM has the capability to identify overlay and tilt signal from a multi-wavelength signal. Scanning electron microscopy (SEM) is a different metrology tool which, to our best knowledge, is instead detecting the two signals as one, without separating them. Overlay and tilt signals identified by IDM can be combined in order to match to SEM - The relative amount of overlay and tilt carried by the IDM signal shows a monotonic and continuous wavelength dependency. These findings increase the understanding of the delta IDM to SEM method, improving the matching between the two. The separation of overly and tilt allows to distinguish which part of the process is causing a certain fingerprint, as tilt is purely driven by non-litho processes. In addition, the combination of overlay and tilt metrology allows improved correlation of the detected AEI signal to yield, and the definition of KPIs for smaller MTD fingerprint. Finally, IDM provides the possibility to keep throughput benefits of optical metrology while overcoming the robustness challenges

Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Fast in-device overlay metrology on multi-tier 3DNAND devices without DECAP and its applications in process characterization and control

Yaobin Feng, Pandeng Xuan, Dean Wu, Bruce Yang, Craig Xu, Neo Liu, Pavel Izikson, Huanian You, Xi-Zhi Yan, Vladimir Markov, Yvon Chai, Chaoyu Chen, Bert Verstraeten, Amy Wang, Gonzalo Sanguinetti, Giacomo Miceli, Jelmer Boter, Vidar Van der Meijden, Hua Li, Babak Mozooni

Proceedings Volume 11611, 116110V (2021) https://doi.org/10.1117/12.2583416

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Proceedings Article | 20 March 2020 Paper

Paper

A novel accurate and robust technique in after-etch overlay metrology of 3D-NAND’s memory holes

Yaobin Feng, Dean Wu, Pandeng Xuan, Pavel Izikson, Payne Qi, Huanian You, Yvon Chai, Jan Jitse Venselaar, Giulio Bottegal, Gonzalo Sanguinetti, Bert Verstraeten, Tjitte Nooitgedagt, Babak Mozooni

Proceedings Volume 11325, 1132522 (2020) https://doi.org/10.1117/12.2553054

KEYWORDS: Optical metrology, Overlay metrology, Semiconducting wafers, Signal processing, Metrology, Machine learning, Image processing, Optical signal processing, Optics manufacturing

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Proceedings Article | 13 March 2018 Presentation + Paper

Presentation + Paper

Holistic metrology qualification extension and its application to characterize overlay targets with asymmetric effects

Olavio Dos Santos Ferreira, Reza Sadat Gousheh, Bart Visser, Kenrick Lie, Rachel Teuwen, Pavel Izikson, Grzegorz Grzela, Babak Mokaberi, Steve Zhou, Justin Smith, Danish Husain, Ram Mandoy, Raul Olvera

Proceedings Volume 10585, 105850T (2018) https://doi.org/10.1117/12.2297184

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Etching, Diffraction gratings, Polarization, Lithography, Diffraction, Optical lithography

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Ever increasing need for tighter on-product overlay (OPO), as well as enhanced accuracy in overlay metrology and methodology, is driving semiconductor industry’s technologists to innovate new approaches to OPO measurements. In case of High Volume Manufacturing (HVM) fabs, it is often critical to strive for both accuracy and robustness. Robustness, in particular, can be challenging in metrology since overlay targets can be impacted by proximity of other structures next to the overlay target (asymmetric effects), as well as symmetric stack changes such as photoresist height variations. Both symmetric and asymmetric contributors have impact on robustness. Furthermore, tweaking or optimizing wafer processing parameters for maximum yield may have an adverse effect on physical target integrity. As a result, measuring and monitoring physical changes or process abnormalities/artefacts in terms of new Key Performance Indicators (KPIs) is crucial for the end goal of minimizing true in-die overlay of the integrated circuits (ICs). IC manufacturing fabs often relied on CD-SEM in the past to capture true in-die overlay. Due to destructive and intrusive nature of CD-SEMs on certain materials, it’s desirable to characterize asymmetry effects for overlay targets via inline KPIs utilizing YieldStar (YS) metrology tools. These KPIs can also be integrated as part of (μDBO) target evaluation and selection for final recipe flow. In this publication, the Holistic Metrology Qualification (HMQ) flow was extended to account for process induced (asymmetric) effects such as Grating Imbalance (GI) and Bottom Grating Asymmetry (BGA). Local GI typically contributes to the intrafield OPO whereas BGA typically impacts the interfield OPO, predominantly at the wafer edge. Stack height variations highly impact overlay metrology accuracy, in particular in case of multi-layer LithoEtch Litho-Etch (LELE) overlay control scheme. Introducing a GI impact on overlay (in nm) KPI check quantifies the grating imbalance impact on overlay, whereas optimizing for accuracy using self-reference captures the bottom grating asymmetry effect. Measuring BGA after each process step before exposure of the top grating helps to identify which specific step introduces the asymmetry in the bottom grating. By evaluating this set of KPI's to a BEOL LELE overlay scheme, we can enhance robustness of recipe selection and target selection. Furthermore, these KPIs can be utilized to highlight process and equipment abnormalities. In this work, we also quantified OPO results with a self-contained methodology called Triangle Method. This method can be utilized for LELE layers with a common target and reference. This allows validating general μDBO accuracy, hence reducing the need for CD-SEM verification.

Proceedings Article | 28 March 2017 Paper

Paper

Reducing the overlay metrology sensitivity to perturbations of the measurement stack

Yue Zhou, DeNeil Park, Karsten Gutjahr, Abhishek Gottipati, Tam Vuong, Sung Yong Bae, Nicholas Stokes, Aiqin Jiang, Po Ya Hsu, Mark O'Mahony, Andrea Donini, Bart Visser, Chris de Ruiter, Grzegorz Grzela, Hans van der Laan, Martin Jak, Pavel Izikson, Stephen Morgan

Proceedings Volume 10145, 101452G (2017) https://doi.org/10.1117/12.2257913

KEYWORDS: Overlay metrology, Metrology, Scatterometry, Environmental sensing, Image processing, Diffraction gratings, Diffraction, Chemical mechanical planarization, Defense and security, Image analysis

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Proceedings Article | 28 March 2017 Paper

Paper

Application of advanced diffraction based optical metrology overlay capabilities for high-volume manufacturing

Kai-Hsiung Chen, Guo-Tsai Huang, Hung-Chih Hsieh, Wei-Feng Ni, S. M. Chuang, T. K. Chuang, Chih-Ming Ke, Jacky Huang, Shiuan-An Rao, Aysegul Cumurcu Gysen, Maxime d'Alfonso, Jenny Yueh, Pavel Izikson, Aileen Soco, Jon Wu, Tjitte Nooitgedagt, Jeroen Ottens, Yong Ho Kim, Martin Ebert

Proceedings Volume 10145, 1014528 (2017) https://doi.org/10.1117/12.2257894

KEYWORDS: Overlay metrology, Metrology, High volume manufacturing, Scatterometry, Diffraction, Optical metrology, Lithography, Process control, Optical lithography, Time metrology, Image registration, Target acquisition, Semiconducting wafers

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Proceedings Article | 20 April 2011 Paper

Paper

Improved overlay control using robust outlier removal methods

John Robinson, Osamu Fujita, Hiroyuki Kurita, Pavel Izikson, Dana Klein, Inna Tarshish-Shapir

Proceedings Volume 7971, 79711G (2011) https://doi.org/10.1117/12.879494

KEYWORDS: Overlay metrology, Data modeling, Metrology, Semiconductor manufacturing, Semiconductors, Semiconducting wafers, Process control, Numerical simulations, Data processing, Instrument modeling

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Proceedings Article | 2 April 2010 Paper

Paper

Automated optimized overlay sampling for high-order processing in double patterning lithography

Chiew-seng Koay, Matthew Colburn, Pavel Izikson, John Robinson, Cindy Kato, Hiroyuki Kurita, Venkat Nagaswami

Proceedings Volume 7638, 76381R (2010) https://doi.org/10.1117/12.846371

KEYWORDS: Semiconducting wafers, Statistical modeling, Lithography, Overlay metrology, Double patterning technology, Photomasks, Optical lithography, Metrology, Data modeling, Mathematical modeling

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Proceedings Article | 2 April 2010 Paper

Paper

Mask registration and wafer overlay

Chulseung Lee, Changjin Bang, Myoungsoo Kim, Hyosang Kang, Dohwa Lee, Woonjae Jeong, Ok-Sung Lim, Seunghoon Yoon, Jaekang Jung, Frank Laske, Lidia Parisoli, Klaus-Dieter Roeth, John Robinson, Sven Jug, Pavel Izikson, Berta Dinu, Amir Widmann, DongSub Choi

Proceedings Volume 7638, 76382I (2010) https://doi.org/10.1117/12.846321

KEYWORDS: Photomasks, Semiconducting wafers, Overlay metrology, Scanners, Pellicles, Metrology, Image registration, Distance measurement, Distortion, Double patterning technology

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Proceedings Article | 10 March 2010 Paper

Paper

Simultaneous optimization of dose and focus controls in advanced ArF immersion scanners

Tsuyoshi Toki, Pavel Izikson, Junichi Kosugi, Naruo Sakasai, Keiko Saotome, Kazuaki Suzuki, Daniel Kandel, John Robinson, Yuji Koyanagi

Proceedings Volume 7640, 764016 (2010) https://doi.org/10.1117/12.846413

KEYWORDS: Semiconducting wafers, Control systems, Finite element methods, Critical dimension metrology, Error analysis, Scanners, Neural networks, Scatter measurement, Scatterometry, Data modeling

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Proceedings Article | 23 March 2009 Paper

Paper

Sampling for advanced overlay process control

Cindy Kato, Hiroyuki Kurita, Pavel Izikson, John Robinson

Proceedings Volume 7272, 727206 (2009) https://doi.org/10.1117/12.813568

KEYWORDS: Semiconducting wafers, Overlay metrology, Process control, Time metrology, Monte Carlo methods, Optical lithography, Statistical methods, Control systems, Immersion lithography, Lithography

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Proceedings Article | 16 April 2008 Paper

Paper

Sampling for advanced overlay process control

DongSub Choi, Pavel Izikson, Doug Sutherland, Kara Sherman, Jim Manka, John Robinson

Proceedings Volume 6922, 69222U (2008) https://doi.org/10.1117/12.772738

KEYWORDS: Overlay metrology, Semiconducting wafers, Process control, Metrology, Time metrology, Scanners, Error analysis, Optical lithography, Lithography, Fourier transforms

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Proceedings Article | 3 April 2008 Paper

Paper

Optimization of high order control including overlay, alignment, and sampling

Dongsub Choi, Chulseung Lee, Changjin Bang, Daehee Cho, Myunggoon Gil, Pavel Izikson, Seunghoon Yoon, Dohwa Lee

Proceedings Volume 6922, 69220P (2008) https://doi.org/10.1117/12.772274

KEYWORDS: Semiconducting wafers, Optical alignment, Overlay metrology, Data modeling, Control systems, Critical dimension metrology, Semiconductors, Process control, Lithography, Nonlinear control

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Proceedings Article | 25 March 2008 Paper

Paper

In-line focus-dose monitoring for hyper NA imaging

Sara Loi, Alejandro Fasciszewski Zeballos, Umberto Iessi, John Robinson, Pavel Izikson, Antonio Mani, Marco Polli

Proceedings Volume 6922, 69223H (2008) https://doi.org/10.1117/12.772904

KEYWORDS: Semiconducting wafers, Metrology, Data modeling, Neural networks, Scanners, Lithography, 3D modeling, Diffractive optical elements, Finite element methods, Photoresist processing

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Proceedings Article | 18 June 2007 Paper

Paper

Differential signal scatterometry overlay metrology: an accuracy investigation

Daniel Kandel, Mike Adel, Berta Dinu, Boris Golovanevsky, Pavel Izikson, Vladimir Levinski, Irina Vakshtein, Philippe Leray, Mauro Vasconi, Bartlomiej Salski

Proceedings Volume 6616, 66160H (2007) https://doi.org/10.1117/12.725929

KEYWORDS: Overlay metrology, Scatterometry, Semiconducting wafers, Detection and tracking algorithms, Computer simulations, Silicon, Standards development, Electromagnetism, Metrology, Algorithms

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Proceedings Article | 5 April 2007 Paper

Paper

45nm design rule in-die overlay metrology on immersion lithography processes

Yu-Hao Shih, George KC Huang, Chun-Chi Yu, Mike Adel, Chin-Chou Kevin Huang, Pavel Izikson, Elyakim Kassel, Sameer Mathur, Chien-Jen Huang, David Tien, Yosef Avrahamov

Proceedings Volume 6518, 651831 (2007) https://doi.org/10.1117/12.711754

KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Scanners, Immersion lithography, Statistical modeling, Optical lithography, Data modeling, Optical alignment, Reticles

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Proceedings Article | 5 April 2007 Paper

Paper

Improved overlay control through automated high order compensation

S. Wakamoto, Y. Ishii, K. Yasukawa, A. Sukegawa, S. Maejima, A. Kato, J. Robinson, B. Eichelberger, P. Izikson, M. Adel

Proceedings Volume 6518, 65180J (2007) https://doi.org/10.1117/12.712710

KEYWORDS: Scanners, Distortion, Databases, Semiconducting wafers, Overlay metrology, Reticles, Control systems, Optical alignment, Lithography, Error analysis

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Proceedings Article | 24 March 2006 Paper

Paper

In-field overlay uncertainty contributors: a back end study

Mike Adel, Aviv Frommer, Elyakim Kassel, Pavel Izikson, Philippe Leray, Bernd Schulz, Rolf Seltmann, Jens Busch

Proceedings Volume 6152, 615213 (2006) https://doi.org/10.1117/12.656467

KEYWORDS: Reticles, Overlay metrology, Scanners, Data modeling, Semiconducting wafers, Metrology, Chemical mechanical planarization, Manufacturing, Polishing, Optical alignment

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Proceedings Article | 24 March 2006 Paper

Paper

AIM technology for nonvolatile memories microelectronics devices

Pier Luigi Rigolli, Laura Rozzoni, Catia Turco, Umberto Iessi, Marco Polli, Elyakim Kassel, Pavel Izikson, Yosef Avrahamov

Proceedings Volume 6152, 61524C (2006) https://doi.org/10.1117/12.656485

KEYWORDS: Overlay metrology, Metrology, Image segmentation, Front end of line, Semiconducting wafers, Chemical mechanical planarization, Metals, Lithography, Scanning electron microscopy, Scanners

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Proceedings Article | 10 May 2005 Paper

Paper

In field overlay uncertainty contributors

Aviv Frommer, Elyakim Kassel, Pavel Izikson, Mike Adel, Philippe Leray, Bernd Schulz

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.599397

KEYWORDS: Reticles, Overlay metrology, Semiconducting wafers, Scanners, Dysprosium, Metrology, Data modeling, Personal protective equipment, Lithography, Manufacturing

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Proceedings Article | 24 May 2004 Paper

Paper

A comparison of methods for in-chip overlay control at the 65-nm node

John Robinson, Mark Stakely, Jorge Poplawski, Pavel Izikson, Elyakim Kassel, Mike Adel

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.534510

KEYWORDS: Overlay metrology, Metrology, Scanners, Error analysis, Reticles, Semiconducting wafers, Personal protective equipment, Lithography, Data modeling, Data acquisition

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Proceedings Article | 24 May 2004 Paper

Paper

Target noise in overlay metrology

Joel Seligson, Mike Adel, Pavel Izikson, Vladimir Levinski, Dan Yaffe

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.534515

KEYWORDS: Overlay metrology, Aluminum, Reticles, Scanners, Metrology, Back end of line, Metals, Semiconducting wafers, Copper, Diagnostics

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Proceedings Article | 24 May 2004 Paper

Paper

Test of a new sub-90-nm DR overlay mark for DRAM production

Stefan Gruss, Ansgar Teipel, Carsten Fuelber, Elyakim Kassel, Mike Adel, Mark Ghinovker, Pavel Izikson

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.534518

KEYWORDS: Overlay metrology, Aluminum, Carbon, Photomasks, Semiconducting wafers, Metrology, Error analysis, Etching, Metals, Reticles

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Proceedings Article | 2 June 2003 Paper

Paper

Characterization of overlay mark fidelity

Mike Adel, Mark Ghinovker, Jorge Poplawski, Elyakim Kassel, Pavel Izikson, Ivan Pollentier, Philippe Leray, David Laidler

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483430

KEYWORDS: Overlay metrology, Semiconducting wafers, Reticles, Chemical mechanical planarization, Statistical analysis, Error analysis, Silicon, Manufacturing, Optical lithography, Metrology

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In this publication we introduce a new metric for process robustness of overlay metrology in microelectronic manufacturing. By straightforward statistical analysis of overlay metrology measurements on an array of adjacent, nominally identical overlay targets the Overlay Mark Fidelity (OMF) can be estimated. We present the results of such measurements and analysis on various marks, which were patterned using a DUV scanner. The same reticle set was used to pattern wafers on different process layers and process conditions. By appropriate statistical analysis, the breakdown of the total OMF into a reticle-induced OMF component and a process induced OMF component was facilitated. We compare the OMF of traditional box-in-box overlay marks with that of new gratingbased overlay marks and show that in all cases the grating marks are superior. The reticle related OMF showed an improvement of 30 % when using the new grating-based overlay mark. Furthermore, in a series of wafers run through an STI-process with different Chemical Mechanical Polish (CMP) times, the random component of the OMF of the new grating-based overlay mark was observed to be 40% lower and 50% less sensitive to process variation compared with Box in Box marks. These two observations are interpreted as improved process robustness of the grating mark over box in box, specifically in terms of reduced site by site variations and reduced wafer to wafer variations as process conditions change over time. Overlay Mark Fidelity, as defined in this publication, is a source of overlay metrology uncertainty, which is statistically independent of the standard error contributors, i.e. precision, TIS variability, and tool to tool matching. Current overlay metrology budgeting practices do not take this into consideration when calculating total measurement uncertainty (TMU). It is proposed that this be reconsidered, given the tightness of overlay and overlay metrology budgets at the 70 nm design rule node and below.

Proceedings Article | 16 July 2002 Paper

Paper

Overlay accuracy in 0.18-micron copper dual-damascene process

Bernd Schulz, Harry Levinson, Rolf Seltmann, Joel Seligson, Pavel Izikson, Anat Ronen

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473477

KEYWORDS: Overlay metrology, Semiconducting wafers, Calibration, Wafer-level optics, Etching, Optical testing, Metrology, Reticles, Scanners, Manufacturing

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Proceedings Article | 16 July 2002 Paper

Paper

Overlay accuracy: a metal layer study

Andrew Habermas, Bradley Ferguson, Joel Seligson, Elyakim Kassel, Pavel Izikson

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473466

KEYWORDS: Etching, Metals, Semiconducting wafers, Overlay metrology, Atomic force microscopy, Diffractive optical elements, Manufacturing, Metrology, Chemical mechanical planarization, Tolerancing

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Showing 5 of 26 publications

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