KEYWORDS: Field programmable gate arrays, Binary data, Computer programming, Logic, Time division multiplexing, Error analysis, Detection and tracking algorithms, Mathematics, Signal processing, Data processing
This paper describes an approach to design and implement a radix-10 online floating-point multiplier. An online
approach is considered because it offers computational flexibility not available with conventional arithmetic. The
design was coded in VHDL and compiled, synthesized, and mapped onto a Virtex 5 FPGA to measure cost in
terms of LUTs (look-up-tables) as well as the cycle time and total latency. The routing delay which was not
optimized is the major component in the cycle time. For a rough estimate of the cost/latency characteristics,
our design was compared to a standard radix-2 floating-point multiplier of equivalent precision. The results
demonstrate that even an unoptimized radix-10 online design is an attractive implementation alternative for
FPGA floating-point multiplication.
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