KEYWORDS: Open source software, Computer simulations, Computer architecture, Signal generators, Information technology, Field programmable gate arrays, Design and modelling, Clocks, Power consumption, Signal processing
Interrupt technology is a key technology for processors to respond to external events and plays an important role in the embedded field. The open source RISC-V architecture defines a complete set of interrupt mechanisms with hardware definitions that do not support interrupt nesting in embedded systems that only support machine mode, and software support for interrupt nesting adds additional time overhead. This paper is based on the interrupt mechanism defined by RISC-V, using a state machine to control the global interrupt enablement of the processor to support interrupt nesting, and to save the site and restore the site through hardware stacking and out-stacking to avoid the time consumption caused by the software level; a dedicated entry point for interrupt service program jumps further speeds up the response. In this paper, we design and implement a fast interrupt system using Hummingbird E203, an open source kernel defined by standard RISC-V, as an experimental platform. Simulation verification and comprehensive implementation on FPGA platform show that compared to the interrupt handling process of Hummingbird E203, using a small amount of hardware resource consumption, the response speed is improved by 1/4, providing better real-time performance and flexibility in embedded applications.
KEYWORDS: Power consumption, Design and modelling, Matrices, Convolutional neural networks, Windows, Clocks, Computer architecture, Convolution, Image compression, Digital signal processing
A low-power RISC-V-based convolutional neural network acceleration processor is proposed to cope with the problem that the increasing resource requirements of convolutional neural networks in the direction of hardware convolutional acceleration are difficult to be met on embedded devices. The processor is designed with three instructions that can configure the parameters of each CNN layer to accommodate different input data, multiplex computational resources to reduce power consumption, and execute operations that repeat a large number of executions in parallel to speed up operation efficiency. Through comparison experiments, it can be found that this processor acceleration instruction set is 20.93 times, 7.67 times, and 8.97 times faster than the base RISC-V instruction set after verified with the same data on three operations, including convolution, activation, and pooling, respectively. The experimental results show that the total power consumption of the processor with this custom instruction set is only 0.221 W at 16 MHZ operating frequency, which is advantageous in terms of performance-to-power ratio compared to other RISC-V accelerated processors with less resource consumption and lower power consumption.
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