CMOS image sensor (CIS) is used in various applications such as surveillance cameras, automobile cameras, mobile phones and digital single lens reflex (DSLR). The photodetectors used in the CIS are p-n junction photodiodes, pinned photodiodes, MOSFET-type photodetectors, and bipolar junction transistor-type photodetectors. A CMOS active pixel sensor (APS) with adjustable sensitivity is presented which uses MOSFET-type photodetector with a built-in transfer gate. The sensitivity of the APS using the MOSFET-type photodetector is much higher than that of the APS using the pn junction photodiode, since the MOSFET-type photodetector is composed of a floating-gate tied to an n-well and the photocurrent is amplified by the MOSFET. Although the APS using conventional MOSFET-type photodetector cannot control the current flowing through the channel, the APS using MOSFET-type photodetector with a built-in transfer gate can control the photocurrent by adjusting the pulse level of the transfer gate. Since the transfer gate controls the amount of electric charge that is transferred from the drain of the MOSFET to the integration node, the sensitivity of the APS can be adjusted by controlling the pulse level of the transfer gate. Using the high sensitivity characteristic of MOSFETtype photodetector and the function of transfer gate, the APS maintains high sensitivity under low intensity of illumination and adjusts to low sensitivity under high intensity of illumination. These results might be useful for extending the dynamic range of the APS using the MOSFET-type photodetector. The CMOS APS was designed and fabricated using 2-poly 4-metal 0.35 μm standard process and its performance was evaluated.
A dynamic range (DR) extension technique based on a 3-transistor (3-Tr.) active pixel sensor (APS) and dual image
sampling has been proposed. The feature of the proposed APS was that the APS used two photodiodes with different
sensitivities, a high-sensitivity photodiode and a low-sensitivity photodiode. Operation of the proposed APS was
simulated by using a 128×128 pixel array. Compared with previously proposed wide DR (WDR) APS, the proposed
approach has several advantages; no-external equipments or signal processing for combining images, no-additional timerequirement
for additional charge accumulation, adjustable DR extension and no temporal disparity.
In this paper, we present a wide dynamic range active pixel sensor (APS) using an external charge pump circuit. The
proposed pixel exhibits improved dynamic range through the compensated threshold voltage of a reset MOSFET. We
confirmed that the light level which is the saturated output voltage in the proposed APS is about 170,000 lux, which is
36% higher than that of a conventional APS. The proposed APS is fabricated by using 2-poly 4-metal 0.35 &mgr; standard
CMOS process. The unit pixel consists of an n+ diffusion / p-substrate photodiode, three NMOSFETs and the charge
pump circuit which consists of two NMOSFETs and two capacitors.
In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The
key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge
accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision
chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the
vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is
commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive
network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a
160×120 pixel array was fabricated using a 0.35 &mgr;m double-poly four-metal CMOS technology, and its operation was
experimentally investigated.
In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate
that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 &mgr;m 2-poly 4-
metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 &mgr;m pixels. The unit pixel has a
configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer
gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer
gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 103 A/W
without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination
as low as 5 lux.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.