Dr. Sherif Hammouda Profile

Dr. Sherif Hammouda

Engineering Director at Siemens EDA

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Publications (4)

Proceedings Article | 23 March 2020 Paper

Approaches for full coverage physical design space exploration and analysis by synthetic layout generation

Marwah Shafee, Joe Kwan, Wael El-Manhawy, Aliaa Kabeel, Sarah Risk, Jongha Park, SeungJo Lee, Jin Hee Kim, Mostafa Alaa, Mohamed Bahnasawi, Abdelrahman Abdelrazek, Sherif Hammouda, Kareem Madkour, Nabil Sabry

Proceedings Volume 11328, 1132808 (2020) https://doi.org/10.1117/12.2551916

KEYWORDS: Metals, Product engineering, Monte Carlo methods, Image classification, Library classification systems, Classification systems, Process engineering, Manufacturing

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Proceedings Article | 27 February 2015 Paper

Toward new design-rule-check of silicon photonics for automated layout physical verifications

Mohamed Ismail, Raghi El Shamy, Kareem Madkour, Sherif Hammouda, Mohamed Swillam

Proceedings Volume 9367, 93671K (2015) https://doi.org/10.1117/12.2078357

KEYWORDS: Waveguides, Photonic integrated circuits, Wave propagation, Silicon photonics, Semiconducting wafers, Electronic design automation, Instrument modeling, Neodymium, Directional couplers, Standards development

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Proceedings Article | 8 November 2012 Paper

Placement-aware decomposition of a digital standard cells library for double patterning lithography

Amr Wassal, Heba Sharaf, Sherif Hammouda

Proceedings Volume 8522, 852222 (2012) https://doi.org/10.1117/12.964381

KEYWORDS: Double patterning technology, Photomasks, Lithography, Standards development, Visualization, Prototyping, Digital electronics, Feature extraction, Photomask technology, Current controlled current source

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To continue scaling the circuit features down, Double Patterning (DP) technology is needed in 22nm technologies and lower. DP requires decomposing the layout features into two masks for pitch relaxation, such that the spacing between any two features on each mask is greater than the minimum allowed mask spacing. The relaxed pitches of each mask are then processed on two separate exposure steps. In many cases, post-layout decomposition fails to decompose the layout into two masks due to the presence of conflicts. Post-layout decomposition of a standard cells block can result in native conflicts inside the cells (internal conflict), or native conflicts on the boundary between two cells (boundary conflict). Resolving native conflicts requires a redesign and/or multiple iterations for the placement and routing phases to get a clean decomposition. Therefore, DP compliance must be considered in earlier phases, before getting the final placed cell block. The main focus of this paper is generating a library of decomposed standard cells to be used in a DP-aware placer. This library should contain all possible decompositions for each standard cell, i.e., these decompositions consider all possible combinations of boundary conditions. However, the large number of combinations of boundary conditions for each standard cell will significantly increase the processing time and effort required to obtain all possible decompositions. Therefore, an efficient methodology is required to reduce this large number of combinations. In this paper, three different reduction methodologies are proposed to reduce the number of different combinations processed to get the decomposed library. Experimental results show a significant reduction in the number of combinations and decompositions needed for the library processing. To generate and verify the proposed flow and methodologies, a prototype for a placement-aware DP-ready cell-library is developed with an optimized number of cell views.

Proceedings Article | 8 November 2012 Paper

Split-it!: from litho etch litho etch to self-aligned double patterning decomposition

Yasmine Badr, Amr Wassal, Sherif Hammouda

Proceedings Volume 8522, 852225 (2012) https://doi.org/10.1117/12.977135

KEYWORDS: Photomasks, Double patterning technology, Etching, Lithography, Computer programming, Metals, Extreme ultraviolet lithography, Design for manufacturing, Solids, Silicon

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