Today's Optical Proximity Correction (OPC) is becoming increasingly complex and necessitates that we
use smaller and smaller grid sizes to produce the fine patterns required. These small grids lead to
significant overhead in data handling and, more importantly, for the tools that will write and inspect the
mask, together making the mask extremely expensive. For two dimensional structures, such as corners, we
have very complex structures using either additive or subtractive OPC features to produce the desired
shape. However, it is unclear whether these structures need to be so perfect for the electrical task they are
intended to perform. In previous work we have created a number of corner type electrical test structures
and applied varying degrees of OPC to both the outer and inner corners of the structures, then printed these
on doped polysilicon and the electrical effect of the OPC was investigated. This work showed that the
electrical effect of OPC on the outer corner was minimal, whereas the inner corner shape had a marked
influence upon the electrical resistance of the circuit feature. However, technology continues to move
forward and polysilicon gates are being replaced by metal gates for 32nm node. Therefore, in this work we
replace the polysilicon with a metal and investigate the size and position of OPC applied to both the outer and inner corners of the structures. The data obtained using the metal structures suggests that as was the case when using polysilicon, OPC on the outside corner has little impact upon a simple circuit's performance, while care should be taken with OPC on the inner corners, particularly with regard to the size of the OPC serifs used.
Today's Optical Proximity Correction (OPC) is becoming increasingly complex and necessitates using smaller and
smaller grid sizes to produce the fine patterns required. These small grids lead to very high overhead in data handling, as
well as for the tools that will write and inspect the mask; which together make masks extremely expensive. For two
dimensional structures such as corners, we use complex structures incorporating either additive or subtractive OPC
features to produce the desired shape. It is unclear though, how precisely the final structures must match the original
design to perform their intended electrical functions. In this work we have created a number of corner type electrical test
structures and applied different degrees of OPC to both the outer and inner corners of the structures. These features were
then printed on doped polysilicon wafers, and the wafers were etched and electrically tested. The electrical effect of OPC
on the outer corner was found to be minimal, whereas the inner corner shape had a significant effect upon the electrical
resistance of the circuit feature. The data suggests that OPC on the outside corner has little impact upon a simple circuit's
performance, but care should be taken with OPC on the inner corners, particularly with regard to the size of the OPC
serifs used.
The National Institute of Standards and Technology (NIST) has a multifaceted program in atomic force microscope
(AFM) dimensional metrology. Three major instruments are being used for traceable measurements. The first is a
custom in-house metrology AFM, called the calibrated AFM (C-AFM), the second is the first generation of
commercially available critical dimension AFM (CD-AFM), and the third is a current generation CD-AFM at
SEMATECH - for which NIST has established the calibration and uncertainties. All of these instruments have useful
applications in photomask metrology.
Linewidth reference metrology is an important application of CD-AFM. We have performed a preliminary comparison
of linewidths measured by CD-AFM and by electrical resistance metrology on a binary mask. For the ten selected test
structures with on-mask linewidths between 350 nm and 600 nm, most of the observed differences were less than 5 nm,
and all of them were less than 10 nm. The offsets were often within the estimated uncertainties of the AFM
measurements, without accounting for the effect of linewidth roughness or the uncertainties of electrical measurements.
The most recent release of the NIST photomask standard - which is Standard Reference Material (SRM) 2059 - was also
supported by CD-AFM reference measurements. We review the recent advances in AFM linewidth metrology that will
reduce the uncertainty of AFM measurements on this and future generations of the NIST photomask standard.
The NIST C-AFM has displacement metrology for all three axes traceable to the 633 nm wavelength of the iodine-stabilized
He-Ne laser. One of the important applications of the C-AFM is step height metrology, which has some
relevance to phase shift calibration. In the current generation of the system, the approximate level of relative standard
uncertainty for step height measurements at the 100 nm scale is 0.1 %. We discuss the monitor history of a 290 nm step
height, originally measured on the C-AFM with a 1.9 nm (k = 2) expanded uncertainty, and describe advances that bring
the step height uncertainty of recent measurements to an estimated 0.6 nm (k = 2). Based on this work, we expect to be
able to reduce the topographic component of phase uncertainty in alternating aperture phase shift masks (AAPSM) by a
factor of three compared to current calibrations based on earlier generation step height references.
Simple electrical test structures have been designed that will allow the characterisation of corner serif forms of
optical proximity correction. The structures measure the resistance of a short length of conducting track with a
right angled corner. Varying amounts of OPC can be applied to the outer and inner corners of the feature and the
effect on the resistance of the track measured. These structures have been simulated and the results are presented
in this paper. In addition a preliminary test mask has been fabricated which has test structures suitable for
on-mask electrical measurement. Measurement results from these structures are also presented. Furthermore
structures have been characterised using an optical microscope, a dedicated optical mask metrology system, an
AFM scanner and finally a FIB system. In the future the test mask will be used to print the structures using a
step and scan lithography tool so that they can be measured on-wafer. Correlation of the mask and wafer results
will provide a great deal of information about the e ects of OPC at the CAD level and the impact on the final
printed features.
This paper presents the use of specially designed electrically testable structures to measure characteristics of alternating aperture phase-shifting masks (altPSM). The linewidths of chrome features on the mask are measured using modified cross-bridge structures, the technique behind this is explained together with the specific designs used to characterise both dense and isolated features. A practical, manufacturable solution to overcoming the problem of the non-conductive anti-reflective chromium oxy-nitride is given and results shown to prove its success. Correlation to more conventional CD measurements reinforce this result. A new technique, to measure the overlay of the second laye, used in the mask manufacture as the mask for the quartz etch establishing the phase shifted areas, is discussed. This entails using capacitive test structures in a progressional offset array to establish the minimum capacitance, indicating the overlay achieved. This technique has the added advantage of removing the errors created by mask sag in overlay metrology tools where the mask is held only at the edge. Results are presented indicating the success of this technique.
This paper presents the development of an electrical SPICE model of a Ferroelectric Liquid Crystal (FLC) on silicon microdisplay. Previous work has investigated the use of an electro-optical SPICE model to simulate the optical response of an FLC cell to a given electrical signal. However, the design of the backplane drive scheme for the display also requires an accurate model of the electrical load represented by an FLC cell. The model presented here provides a good fit to electrical measurement results and, in addition, can be combined with elements of the electro-optical model to allow the optical response of the cell to be modelled at the same time. This paper also presents results of charge collection current measurements which highlight the differences in the behavior of the cell when it is switched between positive and negative voltages and then in the other direction.
This paper presents the use of specially designed electrically testable structures to measure and characterise linewidths on both binary and alternating aperture phase-shifting masks (altPSM). The technique behind the use of these modified cross-bridge structures is explained together with the specific designs used to characterise both dense and isolated features. The practicality of measuring masks with and without anti-reflective chromium dioxide are discussed and the the difference in the repeatability of the measurements is presented. CD SEM measurements of these features are compared with those obtained electrically and an excellent correlation between the electrical dimension (ECD) and the dimension measured both on mask and wafer by SEM is shown.
We report on the integration of computational and control functions with image sensor arrays using commodity CMOS processes. The sensors are highly efficient, high density arrays of photo-diodes, with a minimal overhead of one transistor per pixel. We report production arrays of up to 786 X 576 pixels of 10.5 micrometers pitch in 0.8 micrometers double metal single poly CMOS. We also report techniques presently in development to achieve 7.5 micrometers pitch in the same technology. These sensors are fully self-contained with regard to drive and sense electronics. Typical off-chip needs are limited to a clock crystal, supply regulator and some decoupling capacitors. `Intelligence' is provided in the form of analogue and digital functions integrated on the same chip as the sensors. Such functions can include 8- bit ADC, on-chip exposure control and computational functions to achieve color restoration. Integration of these parts allows us to construct a single chip color camera. Results from a proto-type color CMOS camera system are given. Successful realization of these functions leads to order of magnitude reductions in system cost, size and power-consumption when compared to the CCD alternative.
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