Electron beam-based wafer pattern inspection systems have the major advantage of allowing for the inspection of internal electric properties. However, charge-up of the wafer resulting from the use of an electron beam significantly influences inspection and remains a challenging issue. As an alternative approach to strict charge control, the authors propose a new inspection method that is capable of error-free, one-time inspection for recipe preparation, and which provides high-efficiency defect review and low error ratio inspection. Inspection is carried out at a higher-than-expected sensitivity, and defect candidate images are stored by a defect image analyzer (DIA). After inspection, the stored information contains both actual defects and nuisance defects. The distribution of candidate defects is displayed on a wafer map and the operator reviews the stored images and high-resolution review images on demand in order to check whether defects are true or nuisance defects. If necessary, the operator then adjusts the detection sensitivity and the system re-judges the stored data, displaying the modified wafer map to screen. In this way, the proposed system is robust against sensitivity drift caused by charge-up, and offers efficient, low error ratio inspection.
An electron beam inspection is strongly required for HARI to detect contact and via defects that an optical inspection cannot detect. Conventionally, an e-beam inspection system is used as an analytical tool for checking the process margin. Due to its low throughput speed, it has not been used for in-line QC. Therefore, we optimized the inspection area and developed a new auto defect classification (ADC) to use with e-beam inspection as an in-line inspection tool. A
10% interval scan sampling proved able to estimate defect densities. Inspection could be completed within 1 hour. We specifically adapted the developed ADC for use with e-beam inspection because the voltage contrast images were not sufficiently clear so that classifications could not be made with conventional ADC based on defect geometry. The new ADC used the off-pattern area of the defect to discriminate particles from other voltage contrast defects with an accuracy of greater than 90%. Using sampling optimization and the new ADC, we achieved inspection and auto defect review with throughput of less than 1 and one-half hours. We implemented the system as a procedure for product defect QC and proved its effectiveness for in-line e-beam inspection.
KEYWORDS: Algorithm development, Detection and tracking algorithms, Semiconducting wafers, Inspection, Signal detection, Defect detection, Optical inspection, Digital image processing, Digital signal processing, Wafer-level optics
Algorithms for visual inspection of LSI wafer multilayer patterns have been developed. These algorithms compare corresponding images of two dies on a wafer. In this paper, two algorithms are proposed. The derivative-polarity comparison algorithm compares the polarities of the first derivatives of two images, and recognizes the regions whose polarities are not matched as positional discrepancies (defects), in order to cope with gray-scale differences caused by pattern thickness errors. The multiple-displacement pattern matching algorithm executes the above polarity comparisons at several positions with images suitably aligned, and determines the common unmatched regions as defective, in order to handle the interlayer- registration errors encountered with multilayer patterns. These algorithms were evaluated experimentally, and it was verified that defects of 0.3 micrometers or more can be reliably detected in multilayer patterns by combining these algorithms.
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