KEYWORDS: Nanoimprint lithography, Capacitors, Semiconducting wafers, Optical lithography, Fabrication, Image processing, Scanning electron microscopy, Chemical mechanical planarization, Back end of line, Tungsten
Nanoimprint lithography (NIL) is regarded as a promising technique for application to fabrication of the dual damascene structures that are commonly fabricated in back-end-of-line layers. Initial development work has commenced with a simple single-level process to evaluate the suitability of NIL for back-end processing applications. In this work, a test pattern with a minimum half-pitch of 24nm was patterned using NIL, and W damascene interconnects were then fabricated via a combination of W deposition followed by chemical mechanical polishing. The electrical performances of the test devices were subsequently evaluated using the open/short test element group. The line resistances and leakage currents of the W interconnect structures fabricated using NIL showed good cumulative distributions at the designed minimum linewidth of 24nm. We also demonstrated that a diagonal zigzag capacitor pattern with a pattern size of 2X nm showed good electrical properties.
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