At the 32nm node, the most important issue for mass production in immersion lithography is defectivity control. Many methods have been studied to reduce post-exposure immersion defects. Although a topcoat process demonstrates good immersion defect prevention, a topcoat-less resist process is an attractive candidate for immersion lithography due to cost reduction from a simplified process. In this paper we took the innovative approach of chemically designing an internal self-assembling barrier material that creates a thin embedded layer which functions as a topcoat. Data will be presented on this novel self assembly concept, illustrating the control of leaching, contact angle and immersion defects. Several optimized process flows with non-topcoat resists were also studied to decrease the amount of immersion defects. This study was used to verify the capability of a topcoat-less immersion process to achieve the low-defectivity levels required for 32nm node production.
As the IC product scribe line of logic 90nm (L90) technology shrinks from 80µm to 62μm, the wafer
quality (W.Q.), will become weak and less distinguishable during the subsequent ASML scanner stepper's
photo mask aligning. Many wafers having photo mask aligning errors will eventually lead to wafer
scrapping. In order to improve the photo alignment signal (W.Q.) acquired from the relatively smaller 62μm
scribe-line's alignment mark while proceeding with the VIA layer photo aligning directly to its previous metal
layer, it is found that removing the TiN hard mask (H.M.) just above the previous inter-metal dielectric (IMD)
and alignment mark area can help the deep ultra-violet (DUV) 193nm wavelength ASML scanner stepper
successfully acquires a better alignment signal and alignment accuracy (A.A.).
However, due to copper (Cu) residues and CMP dishing after metal copper CMP, it has been found
that both large area "half size open" and "full size open" approaches for TiN removing in the scribe-line
alignment area can not be used. Hence, for safer photolithography aligning margin the "sizing + 0.25μm"
mark on the scribe line's photo alignment area is suggested for better signal acquiring, whose experimental
results in UMC shows that around 90% of the alignment signal (W.Q.) can be verified. The alignment
accuracy (A.A.) can also be improved through using this technique and is accurate enough as compared to the
conventional scanner alignment method used for above 0.13μm generation technology.
A vertical double gate MOSFET (FinFET) device with an ultra-small poly-Si gate of 30nm and promising
device performances has been successfully developed after integrating a 14Å nitrided gate oxide on
silicon-on-insulator (SOI) wafers. First, a 500Å-thick TEOS capping oxide layer was deposited upon a
1000Å-thick poly-Si gate layer. Second, both 1050Å-thick bottom anti-reflective coating (BARC) and
2650Å-thick photoresist (PR) were coated. A deep ultra-violet (DUV) 193nm wavelength ASML
scanner lithography tool was used for the ultra-small poly-Si layout patterning under high energy
exposure. After an organic-based trimming down plasma etching of both PR and BARC, the TEOS
capping oxide layer was plasma etched in another oxide-based etching chambers without breaking the
plasma etcher's loadlock vacuum. Then, without removing the already plasma patterned and
trim-downed PR and BARC, an in-situ PR/BARC and TEOS hard mask etching was rendered for the
final 1000Å-thick poly-Si gate electrode. The poly-Si etching can be automatically stopped by setting
the over-time etching mode to a few seconds after detecting the endpoint signal of the bottom buried
oxide (BOX) insulating layer. Finally, after PR and BARC plasma as well as additional wet cleaning, an
ultra-narrow poly-Si gate electrode, i.e., after etching inspection (AEI) of 30nm, with its capping TEOS
hard mask was successfully fabricated.
RRC (Reducing resist consumption) coating is widely used to reduce photo resist consumption. By using solvent to
pre-wet the wafer surface, photo resist can be coated on wafer easier than normal coating method. But it also can be the
source of defects. In this study, we found that RRC solvent will induce micro-bubble and cause defects. Different
methods had been tried to solve this kind of micro-bubble defects. Results showed that micro-bubble defects can be
found when the wafer is static during RRC solvent dispense. And the defect map was a ring shape. The diameter of the
rings depended on the RRC solvent dispense amount. Non micro-bubble defect was found, if wafer was spinning during
RRC solvent dispense.
A thin FinFET bulk Si-fin body structure has been successfully fabricated upon bulk-Si wafers through
using 193nm scanner lithography and a composite hard mask etching technique. First, a 100Å-thick
buffer SiO2 layer was thermally grown upon the bulk silicon layer and subsequently a 1200Å-thick SiNx
layer and a 1000Å-thick TEOS SiO2 hard mask layer was chemically vapor deposited to form a
composite hard mask structure of buffer-SiO2/SiNx/TEOS. Second, both 1050Å-thick BARC and
2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the Si-fin
body layout patterning under relatively high exposure energy. This achieves the ADI (after develop
inspection) of 80nm from the original as-drawn Si-fin layout of 110nm. Then, a deep sub-micron
plasma etcher was used for an aggressive P/R and BARC trimming down processing and both the
capping TEOS and CVD-SiNx with its underlying buffer oxide layers were subsequently etched in other
etching plasma chambers, respectively. Resultantly, the AMI (after mask inspection) can reach 60nm.
Subsequently, both the P/R and BARC were removed with a nominal plasma ashing as well as a RCA
cleaning for the final sub-micron Si-fin plasma etching. Eventually, a 60nm-width and 400nm-height
bulk Si-fin body structure can be successfully etched out after a fixed time-mode silicon plasma etching.
A 100Å-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully
integrated with 14Å nitrided gate oxide as well as a 1200Å high-compressive PECVD ILD-SiNx stressing
layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33%
current gain. To achieve a poly-Si gate length target of 400Å (40nm), a 193nm scanner lithography and
an aggressive oxide hard mask etching techniques were used. First, a 500Å-thick TEOS hard mask layer
was deposited upon the 1500Å-thick poly-Si gate electrode. Second, both 1050Å-thick bottom
anti-reflective coating (BARC) and 2650Å-thick photoresist (P/R) were coated and a 193nm scanner
lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then,
a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing
and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the
plasma etcher’s vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA
cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF(aq)
solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick
enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of
40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching,
which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14Å-thick nitrided
gate oxide.
A vertical double gate (FinFET) devices with a high Si-fin aspect ratio of height/width (H/W) = 87nm/11nm have been successfully fabricated on SOI wafers. Firstly, a 50nm-thick capping oxide layer was thermally grown upon the SOI crystalline silicon layer. Secondly, both 105nm-thick BARC and 265nm-thick photoresist were coated and a 193nm scanner lithography tool was used for the Si-fin layout patterning under high ASML exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive photoresist and BARC trimming down processing and the Si-fin capping oxide layer was subsequently plasma etched in another etching chamber without breaking the plasma etcher's loadlock vacuum. Continuously, the photoresist and BARC were removed with a plasma ashing and a RCA cleaning. Also, the patterned Si-fin capping oxide can be further trimmed down with an additional DHF cleaning and the remained ~22nm-thick capping oxide was still thick enough to act as a robust hard mask for the subsequent Si-fin plasma etching. Finally, an ultra thin Si-fin width 11nm and Si-fin height of 87nm can be successfully fabricated through the last silcon plasma etching.
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