William H. Arnold Chief Scientist, and Vice President of Technology Development Center, ASML.
Education MS in Physics, University of Chicago BA in Physics, Hampshire College
Technical Activities/Interests • Optical and EUV lithography; semiconductor devices and chip manufacturing; nanoscale processing for future electronic and photonics devices
Service to the Technical Community • Micro and Nanoengineering (MNE) Organizing Committee, 1998-2010 • International Society of Semiconductor Manufacturers (ISSM) Organizing Committee, 2006-2010 • 193 nm Symposium Organizing Committee, 1995-1998 • 157 nm Symposium Organizing Committee, 1999-2002 • Next Generation Lithography Working Group, 1997-2001 • VLSI Symposium Program Committee, 1998-2000 • SIA Lithography Technical Working Group Co-Chairman 1996-97 • Technical Advisory Board (TAB); Sematech, to define US lithography roadmap, 1988-97; Sematech Lithography Focus TAB Chairman 1992-93 • Member IEEE (since 1992); Member OSA (since 1996) • Author of >100 technical papers, book chapters, and short courses on microlithography and metrology for semiconductor devices • Many book and paper reviews • Numerous invited talks and panels (IEDM, VLSI, VLSI-TSA, ESSDRC)
Services to SPIE • Member of SPIE (since 1983) • Member of SPIE Board of Directors, 2004-2007 • Senior Editor, Microlithography, Journal of Micro/Nanolithography, MEMs, and MOEMs (JM3), 2002-2010 • Advisory Committee Advanced Lithography Symposium - 1988-2010 • Chairman, Publications Committee, 2004-2008 • Publications Committee 2001-2009 • Symposium Committee 1996-1998, 2004-2007 • Frits Zernike Microlithography Award Committee 2002-2004 • Microlithography Symposium – Chairman 1994-95, Vice Chairman 1992-93 • Integrated Circuit Metrology, Inspection, and Process Control – Chairman 1990-1991, Vice Chairman 1988-1989, Conference Committee 1986-1993 • Editor, Integrated Circuit Metrology, Inspection, and Process Control IV, Proc
Publications (21)
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Variations in key device parameters such as gate width, fin height, and storage node aspect ratio can lead to performance variations device to device and within die. Extreme excursions can result in yield loss. Metrology and process control are enablers to detect and keep these variations to within certain bounds. As the features of devices continue to shrink, the allowable tolerances for critical dimensions and overlay errors likewise must shrink, in turn forcing the metrology budgets to shrink in step. At the same time, more data is required per wafer to generate higher order analyses while at the same time greater productivity in terms of silicon area processed in unit time is needed to keep the economics favorable. It is essential we develop the strategies needed for metrology in times of shrinking budgets.
EUVL lithography using high resolution step and scan systems operating at 13.5nm is being inserted in leading
edge production lines for memory and logic devices. These tools use mirror optics and either laser produced
plasma (LPP) or discharge produced plasma (DPP) sources along with reflective reduction masks to
image circuit features. These tools show their capability to meet the challenging device requirements for
imaging and overlay. Next generation scanners with resolution and overlay capability to produce 1X nm (10 nm
class) memory and logic devices are in preparation. Challenges remain for EUVL, the principal of which are
increasing source power enabling high productivity, building a volume mask business encouraging rapid
learning cycles, and improving resist performance so it is capable of sub 20nm resolution.
When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will
be below the k1 limit of 0.25. In this paper, we will explore the capability of using the double pattern technique (DPT)
to extend the resolution capability of the water-based immersion lithography and examine the readiness of EUV to carry
the lithography resolution capability beyond the 32 nm HP.
The DPT, whether done in two litho and etch steps (LELE) or using the side wall spacer and sacrificial layer technique
(SPT), will require significant improvement in CDU and overlay process control performance. We will report the
experimental results in exploring the CDU and overlay performance of the LELE and the SPT options. We will also
demonstrate the need to perform full field and full wafer process corrections to compensate for dual CDU populations
and overlay entangled CDU variations.
Furthermore, we will make an assessment of EUV readiness to further extend the lithography resolution capability
beyond the 32 nm half-pitch.
Double patterning has emerged as the likely lithography technology to bridge the gap between water-based ArF
immersion lithography and EUV. The adoption of double patterning is driven by the accelerated timing of the
introduction of device shrinks below 40nm half pitch, especially for NAND flash. With scaling, increased device
sensitivity to parameter variations puts extreme pressure on controlling overlay and critical dimension uniformity.
Double patterning also makes unique demands on overlay and CDU. Realizing that there is no further increase in NA
past the current 1.35 on the horizon, the focus has shifted from a straight shrink using the newest tool to learning how to
reduce the effective k1 through improvements to the tool's control of CDU and overlay, as well as innovative RET,
mask, and process technology.
In double patterning lithography, CDU and overlay are complex and entangled errors. In an approach where the pattern
is split into two masks and recombined in successive lithography and etch steps, a line or space width is defined by
edges placed at separate masks. In an approach where double patterning is achieved by self-aligned processes, CD error
at the first sacrificial mask will translate into pattern placement errors in the final pattern. In all approaches, it is crucial
to understand how these errors interact so that the combined effects can be minimized through proper tool controls,
mask OPC and split algorithms, and process choices. Without aggressive actions, the complexity of this problem
combined with the economic drawbacks of using multiple masking steps to define critical device layers threaten to slow
overall device shrink rates.
This paper will explore the main sources of critical dimension and overlay errors in double patterning lithography and
will point out directions we may follow to make this an effective manufacturing solution.
Double patterning has emerged as a likely lithography technology to bridge the gap between water-based ArF
immersion lithography and EUV. Water immersion, single exposure lithography is limited to about 40nm half pitch
with NA 1.35. Extension of immersion with high index fluids and glasses is theoretically possible, but faces severe
challenges in technology, economics, and timing. In order to extend water immersion lithography further, much
attention is given to reducing effective k1 to less than 0.25 using double patterning. This paper explores the unique
challenges IC metrology faces to enable double patterning, first in development, then in production.
Optical lithography is continually evolving to meet the ever demanding requirements of the micro - and nano- technology communities. Since the optical exposure systems used in lithography are some of the most advanced and complex optical instruments ever built, they involve ever more complex illuminator designs, nearly aberration free lenses, and hyper numerical apertures approaching unity and beyond. Fortunately, the lithography community has risen to the challenge by devising many inventive optical systems and various methods to use and optimize exposure systems. The recent advancement of water immersion technology into lithography for 193nm wavelengths has allowed the numerical aperture (NA) of lithographic lenses to exceed 1.0 or a hyper-NA region. This allows resolution limits to extend to the 45nm node and beyond with NA>1.3. At these extreme NAs, the imaging within the photoresist is accomplished by not only using water immersion but also using polarized light lithography.
This paper will review the current state-of-the-art in immersion, hyper-NA lithography. We show the latest results and discuss the various phenomena that may arise using these systems. Furthermore, we show some of the advanced image optimization techniques that allow lithographic printing at the physical limits of resolution. In addition, we show that the future of optical lithography is likely to go well beyond the 30nm regime using advancements in 193nm double-patterning technology and/or the use of extreme ultra-violet (EUV) optical systems.
The use of immersion technology will extend the lifetime of 193nm and 157nm lithography by enabling numerical apertures (NA) much greater than 1.0. A definition of effective k1 is derived to assist in comparison of various technologies with differing optical characteristics. The ultimate limits of NA are explored by analysis of polarization effects at the reticle and imaging effects at the wafer. The effect of Hertzian or micro-polarization due to the size of the reticle structures is examined through rigorous simulation. For the regime of interest, 20nm to 50nm imaging, it is found that dense features on the reticle will polarize the light into the TE component upwards of 15%. Below this regime, the light becomes polarized in the TM direction. Additionally, oblique incidence on the reticle, resulting from large system NAs and 4x reduction, will cause PSM phase errors. The use of polarization in the illuminator for imaging will result in substantial gains in exposure latitude and MEF when the NA~1.3 with 45nm lines at 193nm. The end-of-line pullback
for 2-dimensional patterns is reduced by the use of TE polarization in the illuminator. The overall polarization effects increase with decreasing k1. The lower limit of optical lithography can be extended by using source-mask optimization and double exposure to go below the classical resolution limit, i.e., k1<0.25.
0.7X reduction every two years, as required by Moore's Law, has increased the emphasis on low k1 imaging. Low k1 is a way to extend each wavelength one node. However, with low k1 imaging, a significant divide opens between the desires of the chip designer and the realities of lithographic reproduction. As k1 decreases from the safe and comfortable 0.8 value enjoyed in the 1980s, to the more stringent 0.5 adopted in production in the 90s, lithographers had to beg designers to let them do line biasing and place hammerheads at the ends of gates in order to compensate for simple proximity effects like iso-dense bias and line end shortening. Now, in the new millenium, many chip makers have to develop processes that work below 0.4 k1, which brings new tensions between the designer and the lithographer in the forms of design rule restrictions, 2D OPC, forbidden pitches, phase assignments, double exposure decompositions, etc.
Progress in optical lithography continues to pace the development of high speed microprocessors and high density DRAM and flash memories. Continuing progress by optical lithographers has allowed low-cost, volume manufacturing of sub-0.25 micron, high density CMOS devices. With stunning success, entire computer systems are now being placed on a single chip, enabling new, advanced technologies for computation, communications, and entertainment to flourish. This paper outlines the requirements of lithography envisioned in the National Technology Roadmap for Semiconductors currently being renewed for 1997 publication. A possible path for the evolution of optical lithography to 180 nm, and then to 130 nm, is mapped out, allowing promising technologies such as 1X proximity x-ray, extreme ultraviolet projection (EUV), scanning projection electron beam (SCALPEL), or ion projection (IPL) to mature in time to address 100 nm and below.
This paper will consider the challenges facing linewidth metrology as devices shrink to the 100nm level and below, forcing all of us to 'thick small'. Significant improvements are needed in low voltage SEM resolution and measurement reproducibility. The applications of electrical probe metrology should be expanded through clever construction of test devices. Atomic force microscopy offers a novel way to measure feature size, as well as wall profiles and material thicknesses, but suffers from slow scan rates and data acquisition cycles. Advances in AFM need to address more rapid CD measurements and real-time imaging.
In this paper we present results of an algorithm that has been developed which is sensitive to phase defects of 60 degrees on i-line alternating PSMs. This algorithm consists of microcode and software which can be loaded into existing inspection hardware. The algorithm works in die-to-die inspection mode and uses both transmitted and reflected light images to maximize sensitivity. Isolated phase defects missing and misaligned shifter edges. A programmed phase defect test plate was developed to characterize defect detection sensitivity. Detection of 60 degree defects smaller than 0.75 micrometer has been demonstrated with this algorithm. Defect sensitivity characterization and actual production plate defect results are shown.
The critical dimension atomic force microscope (CD-AFM) provides a number of unique capabilities for in-line metrology. In this paper, we evaluate the CD-AFM as a metrology tool and discuss its capabilities and limitations for semiconductor process development and production. We report that linewidth measurements made by the CD-AFM correlate well with those made by all other techniques generally used to measure submicron features, including scanning electron microscopy and electrical probing. Measurement repeatability is limited primarily by changes in probe tip shape with increased use. When the tip is accurately calibrated, this tool provides width, height, and slope data on etched and photoresist features with nanometer resolution. Increased throughput and improved automation may make the CD- AFM a key metrology tool for next-generation process development.
We present an analysis of the cost of ownership for a synchrotron-based x-ray proximity printing system. We consider the total number of lithography tools that would be needed for a 0.25-micron manufacturing plant with 5000 200-mm wafer starts per week. We compare the cost of x ray with that of deep ultraviolet lithography for patterning critical levels. For reference, we calculate costs for the noncritical levels as well. We examine x ray costs as functions of synchrotron under-utilization, of reticle cost and usage, and of throughput. Our analysis indicates that, under the assumptions of identical process yield and throughput, x-ray system costs with a fully utilized synchrotron are competitive with deep ultraviolet costs if the manufacturing product has high volume. For low or moderate volume products deep ultraviolet lithography is cheaper, predominantly because of lower reticle costs. The lack of a strong economic driver for x ray suggests that it is unlikely to be introduced into manufacturing until it is clear that no optical technology can adequately meet production needs.
We present a general analysis of cost of ownership for an integrated circuit production lithography system. We illustrate the method with examples from i-line and deep ultraviolet lithography, as well as soft x-ray projection lithography. Tool utilization is emphasized as well as system throughput. Our analysis suggests that with 20 wafer per hour throughput, which may be attainable with soft x-ray projection lithography, lithography costs will rise to four times today's i-line costs, or higher. In addition to throughput, reticles and photoresist will be cost drivers for this technology.
Optical wafer steppers are used in the fabrication of submicron and subhalf micron integrated circuits. The SIA Technology Roadmap has outlined the major requirements steppers must meet for the 64M and 256Mbit memory generations. These include 0.35 μm and 0.25 μm resolution over 22 and 27 mm square image fields. This article outlines these requirements and explores the impact on wafer stepper design and use. Stepper cost of ownership will be considered including the contribution of the reticle to the overall cost of the process.
Two major trends can be discerned. First, the requirement of 0.25 μm imaging over fields larger than a square inch forces the adoption of step and scan technologies as the cost and size of full field lenses grow noncompetitive. Second, in order to reduce the overall cost of ownership of the photolithography process, the industry is adopting mix-and-match strategies using high NA steppers to print critical mask layers and high speed, low NA, wide field steppers to print non-critical layers.
As the depth of focus of optical steppers grows smaller, it becomes more important to determine the position of best focus accurately and quickly. This paper describes the use of phase-shifted mask technology to form a focus vernier: a phase pattern on the stepper reticle which, when imaged in resist, can give both the magnitude and the direction of the focus error. In this, the focus vernier structure is analogous to 3overlay verniers. Thus the determination of focus error can be treated as an alignment problem in the z-axis. This technique is an improvement on previous schemes for the determination of best focus from resist images as it can indicate both the magnitude of the error and its direction in a single exposure.
Phase-shifted patterns (alternating, 90-degree, and chromeless) have been incorporated into a reticle layout, fabricated with a MEBESR III system, and evaluated experimentally at 365 nm using steppers with numerical aperture (NA) ranging from 0.4 to 0.48 and partial coherence ranging from 0.38 to 0.62. Test circuit layouts simulate actual circuit designs with critical dimensions ranging from 0.2 micrometers to 1.2 micrometers . These results, combined with experimental measurement of layer to layer registration and aerial image simulations, provide a first-order assessment of e-beam lithography requirements to support phase-shift mask technology.
Results are presented from a new high numerical aperture (NA 0. 48) iline 5X reduction lens which resolves 0. 5 micron lines and spaces over greater than 1 micron depth of focus in several commercially available i-line resists. The performance of this lens is contrasted with that of a NA 0. 40 i-line lens. The NA 0. 40 lens has better depth of focus for 0. 7 microns lines and spaces (L/S) and larger while the NA 0. 48 lens has better depth of focus for L/S smaller than 0. 7 microns down to a resolution cutoff near 0. 35 micron L/S. Other characteristics of the lens such as its relative insensitivity to absorption heating effects and its behavior as a function of the overpressure of He gas within the lens are explored. Simulation work suggests that a NA of between 0. 5 and 0. 55 is optimum for printing 0. 5 micron L/S. Further it suggests that there may be sufficient depth of focus at 0. 4 micron L/S to make i-line a competitor to DUV lithography for the 64 Mbit DRAM generation. 1.
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