A. Aliane, F. De Moro, P. Agnese, C. Pigot, J.-L. Sauvageot, V. Szeflinski, A. Gasse, M. Arnaud, X. de la Broïse, X.-F. Navick, J. Routin, L. Mathieu, J.-C. Cigna, F. Berger, H. Ribot, Y. Gobil
Several successful development programs have been conducted on Infra-Red bolometer arrays at the French
Atomic Energy Commission (CEA-LETI Grenoble), in collaboration with the CEA-Sap (Saclay); taking
advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation
space astronomy missions, using silicon technology. We have developed monolithic silicon micro-calorimeters
based on implanted thermistors. These micro-calorimeter arrays will be used for future space missions. A 8×8
array prototype consisting of a grid of 64 suspended pixels on SOI (Silicon On Insulator) has been created. Each
pixel of this array detector is made of a tantalum (Ta) absorber and is bonded, by means of an indium bump
hybridization process, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective
process step. The fabrication process of our detector involves a combination of standard silicon technologies
such as Si bulk micromachining techniques, based on deposition, photolithography and plasma etching steps.
Finally, we present the results of measurements performed on the different building elements and processes that
are required to create a detector array up to 32*32 pixels in size.
This paper is focused on the development of silicon dioxide dry etching for Microsystems application. New requirements for oxide etching have been identified; keys issues are the higher oxide thickness (several microns) and the different design rules (large open areas, isolated patterns). To achieve these requirements, advanced oxide etching processes have been developed in conventional reactor using either photoresist or hard mask. The effects of several process parameters on etch rate, selectivity, oxide pattern profile have been investigated. When using a photoresist mask, the major process limitation is caused by the oxide to photoresist selectivity. Straight profiles may only be obtained if the polymerisation on the side-walls is well-controlled. So, a compromise has to be made between etch rate, oxide to mask selectivity and pattern profiles. The use of hard mask leads to achieve excellent profile control with very high aspect ratio. But, gas chemistry and process parameters such as pressure, total gas flow and chemistry have to be precisely adjusted in order to avoid the aspect ratio dependant etching in narrow patterns. Vertical profiles in high aspect ratio features can be achieved but lateral oxide erosion have to be drastically controlled.
BARC technology, originally developed for gate level has now to be applied to interconnection one's. Requirements for dielectric interconnection levels are different from gate level. In the case of gate level ARC has to minimize reflectivity at resist/substrate interface due to notching and resist swing curve effects. Whereas ARC for interconnections has to minimize reflectivity variation at resist/substrate interface due to swing curve effect in the dielectric layer. For interconnections, ARC must be as absorbent as possible at stepper exposure wavelength, and two ways are foreseen: ARC layer with high k value at 248 nm, and ARC layer with high thickness. For a reflectivity variation minimum criteria, we can find a couple values (k, minimum thickness). Experiments give us for a reflectivity variation below 5% the following couples: (k equals 0.7, 1200 Angstrom thickness) and (k equals 1.1, 850 Angstrom). In this paper we describe different applications of SiOxNy for interconnection levels: via, contact and damascene line level. Improvements depending of the SiOxNy thickness are seen in CD dispersion. To conclude SiOxNy ARC can be used for interconnection levels, and its performances depends on ARC couple values (k, thickness).
BARC technology, originally developed for gate level has now to be applied to interconnection one's. Requirements for dielectric interconnection levels are different from gate level. In the case of gate level ARC has to minimize reflectivity at resist/substrate interface due to notching and resist swing curve effects. Whereas ARC for interconnections has to minimize reflectivity variation at resist/substrate interface due to swing curve effect in the dielectric layer. For interconnection, ARC must be as absorbent as possible at stepper exposure wavelength, and two ways are foreseen: ARC layer with high k value at 248 nm, and ARC layer with high thickness. For a reflectivity variation minimum criteria, we can find a couple values (k, minimum thickness). Experiments give us for a reflectivity variation below 5% the following couples: (k equals 0.7, 1200 angstroms thickness) and (k equals 1.1, 850 angstroms). In this paper we describe different applications of SiOxNy for interconnection levels: via, contact and damascene line level. Improvements depending of the SiOxNy thickness are seen in CD dispersion. To conclude SiOxNy ARC can be used for interconnection levels, and its performance depends on ARC couple values (k, thickness).
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