Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

Krzysztof Kasinski; Weronika Zubrzycka

doi:10.1117/12.2249137

28 September 2016 Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

Krzysztof Kasinski, Weronika Zubrzycka

Proceedings Volume 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016; 100313N (2016) https://doi.org/10.1117/12.2249137
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 2016, Wilga, Poland

Abstract

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

Citation Download Citation

Krzysztof Kasinski and Weronika Zubrzycka "Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification", Proc. SPIE 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 100313N (28 September 2016); https://doi.org/10.1117/12.2249137

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