Paper
17 May 1989 An Ultra-Fast SBNR Divider
Michael Andrews, Wayne Lenius
Author Affiliations +
Proceedings Volume 1058, High Speed Computing II; (1989) https://doi.org/10.1117/12.951686
Event: OE/LASE '89, 1989, Los Angeles, CA, United States
Abstract
A novel redundant number system divider chip is described. This design incorporates an SRT division algorithm with internal signed digit representations in the division recurrence loop. The design promises to be faster and requires less physical space.
© (1989) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Andrews and Wayne Lenius "An Ultra-Fast SBNR Divider", Proc. SPIE 1058, High Speed Computing II, (17 May 1989); https://doi.org/10.1117/12.951686
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KEYWORDS
Binary data

Logic

Signal processing

Very large scale integration

Logic devices

Transistors

Multiplexers

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