Paper
20 March 2018 Patterning method impact on sub-36nm pitch interconnect variability
Nicholas V. LiCausi, James C.-H. Chen, R. S. Smith, E. Todd Ryan
Author Affiliations +
Abstract
As advanced semiconductor technologies continue to shrink, there is a continued need for interconnect performance and variability to keep pace. Traditional area scaling alone cannot control the increased process variation at advanced nodes. We examine the impact that patterning scheme has on the final interconnect resistance, capacitance and RC variability at sub-36nm pitches. Industry standard patterning schemes are evaluated using the Monte Carlo method. Single exposure (direct print), litho-etch-litho-etch, self-aligned double patterning and self-aligned quadruple patterning (SAQP) are considered. In the context of these patterning schemes, lithographic variation and spacer thickness uniformity (where applicable) are evaluated.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Nicholas V. LiCausi, James C.-H. Chen, R. S. Smith, and E. Todd Ryan "Patterning method impact on sub-36nm pitch interconnect variability", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058804 (20 March 2018); https://doi.org/10.1117/12.2297117
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Cited by 1 scholarly publication and 1 patent.
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KEYWORDS
Optical lithography

Monte Carlo methods

Resistance

Capacitance

Lithography

Line edge roughness

Line width roughness

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