Presentation + Paper
3 October 2018 EUV pupil optimization for 32nm pitch logic structures
Author Affiliations +
Abstract
A pupil optimization was carried out for the M2 layer of the imec N7 (foundry N5 equivalent) logic design. This is exposed as a single print EUV layer. We focused on the printability of the toughest parts of the design: a dense line space grating of 32 nm pitch and a tip-tip grating of 32 nm pitch, tip-to-tip target CD of 25 nm. We found that the pupil optimization can improve both the line space and the tip-to-tip gratings energy latitude and depth of focus. The tip-to-tip target CD can be pushed further, enabling further design scaling.
Conference Presentation
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
D. Rio, V. Blanco, J.-H. Franke, W. Gillijns, M. Dusa, E. De Poortere, P. Van Adrichem, K. Lyakhova, C. Spence, E. Hendrickx, S. Biesemans, and K. Nafus "EUV pupil optimization for 32nm pitch logic structures", Proc. SPIE 10809, International Conference on Extreme Ultraviolet Lithography 2018, 108090N (3 October 2018); https://doi.org/10.1117/12.2503321
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Source mask optimization

Semiconducting wafers

Scanners

Logic

Extreme ultraviolet lithography

Reticles

Extreme ultraviolet

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