Machine learning based wafer defect detection

Yuansheng Ma; Feng Wang; Qian Xie; Le Hong; Joerg Mellmann; Yuyang Sun; Shao Wen Gao; Sonal Singh; Panneerselvam Venkatachalam; James Word

doi:10.1117/12.2513232

20 March 2019 Machine learning based wafer defect detection

Yuansheng Ma, Feng Wang, Qian Xie, Le Hong, Joerg Mellmann, Yuyang Sun, Shao Wen Gao, Sonal Singh, Panneerselvam Venkatachalam, James Word

Author Affiliations +

Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096208 (2019) https://doi.org/10.1117/12.2513232
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

Detecting and resolving the true on-wafer-hotspot (defect) is critical to improve wafers’ yield in high volume manufacturing semiconductor foundries. Traditionally, Optical Rule Check (ORC) with computation lithography has been one of the most important techniques to flag potential failure patterns (weak points) after Optical Proximity Correction (OPC), where ORC results are fed back to the OPC team to fix the OPC solution if needed, or fed forward to Contamination Free Manufacturing (CFM) team to improve the inspection accuracy. However, as the integrated circuits process becomes more and more complex with the technology scaling, ORC alone could no longer identify the outlier-alike defects, even though it has helped in resolving most of defects on wafer. Failing to detect yield-killer defects could be due to the lack of sufficient understanding and modeling in terms of etching, CMP, as well as other inter-layer process variations. It has been a struggle for Fab to identify reasonable amount of defects scattered on wafer in order to understand defect mechanisms quickly, thus find ways to fix them in a timely manner. In this paper, we present a fast and accurate Defect Detection and Repair Flow (DDRF) with machine learning (ML) methodology to address the above issues. There are four parts in the DDRF: the first part is on the feature generation and data collection, the second on the ML model building, the third on the full-chip prediction, and the fourth on the hot-spot repair. We use limited amount of known defects found on wafer as input to train the ML model, and then apply the ML model to the full chip for prediction. The wafer verification data showed that our flow achieved more than 80% of defect hit rate with engineered feature extractions and ML model for a 7nm mask. Finally, we analyze the failing mechanism with more available defects, and are able to provide guidance to the OPC development to fix the defects by using the ML model.

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Citation Download Citation

Yuansheng Ma, Feng Wang, Qian Xie, Le Hong, Joerg Mellmann, Yuyang Sun, Shao Wen Gao, Sonal Singh, Panneerselvam Venkatachalam, and James Word "Machine learning based wafer defect detection", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096208 (20 March 2019); https://doi.org/10.1117/12.2513232

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