Copper interconnect topography simulation in 3D NAND designs

Yang Li; Rick Li; Peng Jiang; Luming Fan; Aman Zheng; Sicong Wang; Guangyi Wang; Zhengfang Liu; Chunshan Du; Ruben Ghulghazaryan; Qijian Wan; Xinyi Hu

doi:10.1117/12.2515161

20 March 2019 Copper interconnect topography simulation in 3D NAND designs

Yang Li, Rick Li, Peng Jiang, Luming Fan, Aman Zheng, Sicong Wang, Guangyi Wang, Zhengfang Liu, Chunshan Du, Ruben Ghulghazaryan, Qijian Wan, Xinyi Hu

Author Affiliations +

Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096210 (2019) https://doi.org/10.1117/12.2515161
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers stacking, but also for the chip bonding process. As the link between design and manufacturing, design for manufacturing (DFM) predicts potential manufacturing issues during the design stage, enabling design teams to modify the layout and mitigate the risk. The copper interconnect process can be modeled through multiple process steps, from film stacking, etch, and copper deposition to polishing. The simulated topology of a given design predicts potential risky areas that may be fixed by changing designs or inserting dummy fill prior to manufacturing. This simulation is a useful technique during yield ramp-up, and can shorten the cycle from design to manufacturing. This paper presents a solution for BEOL CMP modeling and analysis on BEOL copper interconnect of a 3D NAND flow.

Citation Download Citation

Yang Li, Rick Li, Peng Jiang, Luming Fan, Aman Zheng, Sicong Wang, Guangyi Wang, Zhengfang Liu, Chunshan Du, Ruben Ghulghazaryan, Qijian Wan, and Xinyi Hu "Copper interconnect topography simulation in 3D NAND designs", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096210 (20 March 2019); https://doi.org/10.1117/12.2515161

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