Metrology for advanced transistor and memristor devices and materials

Alain C. Diebold; Nathaniel C. Cady

doi:10.1117/12.2554477

20 March 2020 Metrology for advanced transistor and memristor devices and materials

Alain C. Diebold, Nathaniel C. Cady

Author Affiliations +

Proceedings Volume 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV; 1132502 (2020) https://doi.org/10.1117/12.2554477
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

As scaling becomes more challenging, new approaches to transistor design, new materials, and new devices are all being explored. Advanced transistor designs such as vertically stacked nanowire and nanosheet FETs (NW/NS FETs) provide a pathway to sub-10 nm devices. Ferroelectric High κ enables extension of FinFET and NW/NS FETs as well as providing a potential dielectric for memristive devices, including RRAM and ferroelectric tunnel junctions. NW/NS FETs provide a significant challenge for both processing and process control due to the geometries associated with their 3D structure. Increasing computational power will ultimately require more than scaling, however. Neuromorphic (brain like) computing and non-Von Neumann computing architectures are now being explored as alternative options for increasing computation capability. To develop efficient neuromorphic and non-Von Neumann hardware, new devices and materials integration strategies are required. This paper provides an overview of advanced NW/NS transistors and new memristor devices and materials and their characterization and metrology.

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Alain C. Diebold and Nathaniel C. Cady "Metrology for advanced transistor and memristor devices and materials", Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 1132502 (20 March 2020); https://doi.org/10.1117/12.2554477

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KEYWORDS

Transistors

Field effect transistors

Oxides

Etching

Scatterometry

Crystals

Metrology

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