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In order to fully utilize the potential of the latest and greatest scanner overlay performance capability in a manufacturing environment, all other (process-induced) overlay contributors should be well understood and eliminated where possible. While overlay penalties that slowly vary across the wafer and/or within each exposure field can easily be corrected with the available scanner correction knobs, this is less likely going to happen for overlay signatures that manifest themselves on a much shorter length scale. We refer to length scales that are comparable to the floorplan of the integrated circuit itself. A deep understanding of these process induced overlay contributions is required to take away their root causes. Several non-scanner overlay contributors are known that may have an impact on the scanner exposure field overlay performance. Of course, the quality of the mask itself plays an important role. Mask writing errors correlate one-to-one with the on-wafer overlay performance. Local stress effects may contribute to the intra-die overlay performance too. We extensively addressed the layer stress impact on the intra-field overlay in an earlier publication. In that work, an interesting observation was made. The etch-induced overlay contribution turned out to be largely independent of the layer stress in which the pattern was etched. The conclusion was drawn that the etch-induced overlay penalties can be optimized separately from layer stress related overlay effects. In this work, the focus will be on the etch-induced overlay penalties only. We addressed the etch-induced overlay impact already before. Surprisingly, the etch-induced overlay penalties showed up in every exposure field despite the fact that the etch tool itself is not exposure field aware. For the use-case we investigated, the magnitude of the etch-induced intra-field overlay penalty was around 1-nm. This comes close to the scanner baseline overlay performance. A relation was found with the pattern density distribution and a dependency with the etch tool settings was observed. We identified the Spin-On-Glass and/or Spin-On-Carbon (Hard Mask) etch as the potential root cause. A hypothesis was proposed that was in line with the experimental observations. In this experimental work, we have continued the investigation by validating the hypothesis proposed earlier. Since the hypothesis was based on the pattern density distribution within the exposure field in combination with the deflection of ions due to surface charging effects, both the mask and the etch tool recipe settings per layer have been changed. We show that the etch-induced intra-field overlay penalties can indeed be controlled by changing the etch tool recipe settings per layer. However, the underlying mechanism turned out to be different from what we expected. In the current paper, we will present a new concept that much better explains all the experimental results we have obtained so far. Based on this new understanding, we experimentally demonstrate that etch-induced intra-field overlay penalties can be mitigated by optimizing the etch tool recipe settings.
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