1.

INTRODUCTION

In recent years, mature node demand has surged causing a wafer capacity expansion. There are a myriad of reasons for the surge in global wafer volume increase (Figures 1A and 1B) [1]. Supply chain regionalization and geopolitics, including ~$300B in incentives from various global governments is one reason. These programs are intended to support increasing local electrification and digitalization. Semiconductor products including chiplets, advanced packaging, ASIC wave devices, silicon photonics, quantum computing, virtual reality (VR), and AI designed chips are the new technology that utilizes mature wafer processes. Unfortunately, mask makers are challenged to support the demand increase due to capacity issues. Legacy mask equipment used to manufacture mature devices is reaching end of life (EOL) rapidly. It is imperative that mask makers find ways to integrate new, low cost, equipment with the older generation of tools as they transition to EOL.

Figure 1:

(A) Volume ramp by wafer application category through 2030, (B) Mature device type ramp through 2030.

Here, we discuss the use of advanced data modeling techniques to meet the needs of new mature node technologies as well as extend mask tool sets nearing EOL. Mask makers must continue to face the same challenges with mainstream masks as in the past: high volume and low cost manufacturing to meet modest CD, registration, and defect requirements. The new technologies listed above introduce a new problem for mainstream mask manufacturing. That is a high level of design complexity. In this paper, we will focus on 2 product categories: 1. AI-generated ICs (Figure 2A) [2], and 2. Silicon photonics (Figure 2B) [3]. Both are highly complex for mature mask technology. There are a lack of design for manufacturability (DFM) guardrails resulting in, for example, excessive use of curvilinear features. Most masks are used in I-line or KrF lithography and have narrow process windows.

Figure 2:

(A) Silicon photonics device, (B) AI generated device design.

2.

DISCUSSION

The question we investigate here is whether or not these new mature node designs can benefit from the advanced mask manufacturing flow. Figure 3 depicts the elements of the flow. These including feed forward analysis and corrections such spatial domain analysis using as mask rule check (MRC) to define the design space on the mask and application of mask process correction (MPC) to the data before write. Feedback loop items such as global CDU correction and MPC model maintenance are also part of the continuum.

Figure 3:

Advanced mask manufacturing data flow.

Figure 4 describes the toolkit of corrections available [4][5][6]. These include dose modulation, GCDU correction, corner rounding treatment of 2D features, rules based MPC and model based MPC for process matching.

Figure 4:

Advanced mask data toolkit.

3.

RESULTS

Here, we will discuss the results from application of a few of these advanced techniques to mature node masks. Figure 5 shows the application of machine learning (ML) model to resolve tightened CDU specs for the new designs in mature nodes. Writers for mature masks, typically laser writers, do not have built-in GCDU correction applications as do 50keV generation ebeam writers. When we apply similar principles to the write data, we can improve the GCDU results. A use case was found in a particular ASIC design where the writer was not capable of meeting the GCDU spec (CD range <24nm) reliably. Applying the ML model resulted in a yield improvement from ~45% to >95%.

Figure 5:

Machine learning based GCDU correction.

Another important tool in the kit is MPC. As mentined earlier, MPC can be used for process matching. For commercial mask makers, it is important to be able to increase capacity by qualifying multiple manufacturing sites with disperate toolsets. Figure 6 shows the results of using MPC to cross-qualify an Asian site to match the POR site in the US.

Figure 6:

(A) Linearity of the POR site vs the matching site before MPC correction and (B) the same data after correction.

New mature mask technologies are beginning to utilize complex resolution enhancement techniques (RET) previously only needed for advanced ArF lithography. Spatial domain analysis (SDA) is an important tool to understand what is on the mask before manufacture. As depicted in Figure 7, MRC of the incoming order is performed and analyzed to to understand mask complexity and determine the best manufacturing strategy.

Figure 7:

Spatial domain analysis of an incoming order with complex OPC.

In addition to process matching, MPC can be used to extend process capabilities to enable the continued productive use of legacy toolsets. As mentioned earlier, laser writers commonly used in mature node mask making do not have the same capabilities to make corrections to CDU (local or global) or iso/dense bias that the 50keV ebeam tools have. Figure 8 shows a case of an ASIC processor layer in which MPC enabled manufacture with a laser writer.

Figure 8:

MPC enables capability on an older laser writer.

MPC can also be used to improve pattern fidelity. Figure 9 shows the results of a rules based MPC corner rounding treatment applied to the write data.

Figure 9:

MPC corner rounding treatment.

4.

CONCLUSION

Mature nodes are seeing new challenging designs, with IoT, newer technologies and design methodologies. Expanding volume is predicted requiring mask makers to increase mature mask making capacity with an aging, close to end of life, toolset. Here, we have shown that advanced data analysis and modelling is critical to help maintain the HVM mask capacity and capability for mature nodes. We showed several examples for data analysis, corrections and modeling that helped increasing yield on the new designs. We also demonstrated the readiness to match processes across sites. We used data methods to enable efficient integration of tools into mature nodes HVM to support the increased volume.