A hardware-efficient silicon electronic-photonic chip for optical structured neural networks

Shupeng Ning; Jiaqi Gu; Chenghao Feng; Rongxing Tang; Hanqing Zhu; David Z. Pan; Ray T. Chen

doi:10.1117/12.3000787

11 March 2024 A hardware-efficient silicon electronic-photonic chip for optical structured neural networks

Shupeng Ning, Jiaqi Gu, Chenghao Feng, Rongxing Tang, Hanqing Zhu, David Z. Pan, Ray T. Chen

Proceedings Volume 12892, Optical Interconnects XXIV; 1289204 (2024) https://doi.org/10.1117/12.3000787
Event: SPIE OPTO, 2024, San Francisco, California, United States

Abstract

Optical neural networks (ONNs) have gained significant attention as a promising neuromorphic framework due to their high parallelism, ultrahigh inference speeds, and low latency. However, the hardware implementation of ONN architectures has been limited by their high area overhead. These architectures have primarily focused on general matrix multiplication (GEMMs), resulting in unnecessarily large area costs and high control complexity. To address these challenges, we propose a hardware-efficient architecture for optical structured neural networks (OSNNs). Through experimental validation using an FPGA-based photonic-electronic testing platform, our neural chip demonstrates its effectiveness in on-chip convolution operations and image recognition tasks, which exhibits lower active component usage, reduced control complexity, and improved energy efficiency.

Conference Presentation

Citation Download Citation

Shupeng Ning, Jiaqi Gu, Chenghao Feng, Rongxing Tang, Hanqing Zhu, David Z. Pan, and Ray T. Chen "A hardware-efficient silicon electronic-photonic chip for optical structured neural networks", Proc. SPIE 12892, Optical Interconnects XXIV, 1289204 (11 March 2024); https://doi.org/10.1117/12.3000787

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