Single-qubit randomized benchmarking of flux-tuneable transmons: a test time analysis

Thorsten Last; Yevheniia Cheipesh; Konstantin Lehman; Vraj Patel; Sebastian Hähnle; Timo van Abswoude; Adam Lawrence; Anna Shchygol; Kelvin Loh; Garrelt Alberts; Adriaan Rol

doi:10.1117/12.3009887

9 April 2024 Single-qubit randomized benchmarking of flux-tuneable transmons: a test time analysis

Thorsten Last, Yevheniia Cheipesh, Konstantin Lehman, Vraj Patel, Sebastian Hähnle, Timo van Abswoude, Adam Lawrence, Anna Shchygol, Kelvin Loh, Garrelt Alberts, Adriaan Rol

Author Affiliations +

Proceedings Volume 12955, Metrology, Inspection, and Process Control XXXVIII; 129551W (2024) https://doi.org/10.1117/12.3009887
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.

Conference Presentation

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Thorsten Last, Yevheniia Cheipesh, Konstantin Lehman, Vraj Patel, Sebastian Hähnle, Timo van Abswoude, Adam Lawrence, Anna Shchygol, Kelvin Loh, Garrelt Alberts, and Adriaan Rol "Single-qubit randomized benchmarking of flux-tuneable transmons: a test time analysis", Proc. SPIE 12955, Metrology, Inspection, and Process Control XXXVIII, 129551W (9 April 2024); https://doi.org/10.1117/12.3009887

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