CCD clock register modeling

Thorsten Graeve; Laurence M. Flath; Eustace L. Dereniak

doi:10.1117/12.135923

12 August 1992 CCD clock register modeling

Thorsten Graeve, Laurence M. Flath, Eustace L. Dereniak

Proceedings Volume 1656, High-Resolution Sensors and Hybrid Systems; (1992) https://doi.org/10.1117/12.135923
Event: SPIE/IS&T 1992 Symposium on Electronic Imaging: Science and Technology, 1992, San Jose, CA, United States

Abstract

This paper discusses the design of an RC network model of the parallel clock registers on a charge coupled device. A model has been developed that takes into account the individual pixel capacitance and resistance of the device the line resistance of the polysilicon clock lines and the line-to-line capacitance between adjacent phases. This RC network forms a lossy transmission line that degrades the clock pulses applied to the device as they travel to its center. In the case of high-speed large area CCDs the deterioration in pulse shape can lead to a significant drop-off in charge transfer efficiency (CTE) as a function of distance from the edge of the device. Using SPICE the parallel clock registers of three different CCDs have been simulated. The first device is a large area scientific imager designed to run at relatively slow clock rates. The second CCD is an upgraded version of that device. It includes Aluminum-strapped clock lines to reduce the RC time constant of the clocking structure. The third device is an infrared PtSi imager. The results of the SPICE simulations are used to find the limiting RC time constant of each device and to project its performance as a high-speed imager. 1 .

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Thorsten Graeve, Laurence M. Flath, and Eustace L. Dereniak "CCD clock register modeling", Proc. SPIE 1656, High-Resolution Sensors and Hybrid Systems, (12 August 1992); https://doi.org/10.1117/12.135923

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KEYWORDS

Clocks

Electrodes

Charge-coupled devices

Capacitance

Imaging systems

Resistance

Systems modeling

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