Single-cycle lithography process for both large and sub-half-micron features (Poster Paper)

James S. Sewell; Christopher A. Bozada; Mercy H. Styrcula; William E. Davis; Ross W. Dettmer; Robert A. Neidhart

doi:10.1117/12.136020

9 July 1992 Single-cycle lithography process for both large and sub-half-micron features (Poster Paper)

James S. Sewell, Christopher A. Bozada, Mercy H. Styrcula, William E. Davis, Ross W. Dettmer, Robert A. Neidhart

Proceedings Volume 1671, Electron-Beam, X-Ray, and Ion-Beam Submicrometer Lithographies for Manufacturing II; (1992) https://doi.org/10.1117/12.136020
Event: Microlithography '92, 1992, San Jose, CA, United States

Abstract

The definition of sub-half-micron gates for gallium arsenide (GaAs)-based field effect transistors is generally performed by direct write electron beam lithography (EBL). Because of throughput limitations in defining large geometries by EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We report a new hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire metallization/lift-off process sequence. This technique has been successfully applied to metal semiconductor field-effect transistor wafers containing devices with dual 0.25 X 75 micron gates connected to 75 X 75 micron gate pads by 5 X 25 micron interconnects. The yields on these wafers have been very high with transistors averaging cutoff frequency values of 42 GHz and transconductance values of 366 mS/mm. Thus, the gate-layer process has been simplified without loss in yield or device performance. We will discuss the entire EBOL process technology including the multi-layer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, and comparison to the standard gate-layer process.

Citation Download Citation

James S. Sewell, Christopher A. Bozada, Mercy H. Styrcula, William E. Davis, Ross W. Dettmer, and Robert A. Neidhart "Single-cycle lithography process for both large and sub-half-micron features (Poster Paper)", Proc. SPIE 1671, Electron-Beam, X-Ray, and Ion-Beam Submicrometer Lithographies for Manufacturing II, (9 July 1992); https://doi.org/10.1117/12.136020

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