Optimum field-size strategy for DRAM mass production in low-k1 process

Chan-Ha Park; Donggyu Yim; Seung-Hyuk Lee; Hyun-Jo Yang; Jae-Hak Choi; Yong-Chul Shin; Choi-Dong Kim; Jae-Sung Choi; Khil-Ohk Kang; Sang-Wook Kim; Dong-Duk Lee; Gyu-Han Yoon

doi:10.1117/12.435634

14 September 2001 Optimum field-size strategy for DRAM mass production in low-k1 process

Chan-Ha Park, Donggyu Yim, Seung-Hyuk Lee, Hyun-Jo Yang, Jae-Hak Choi, Yong-Chul Shin, Choi-Dong Kim, Jae-Sung Choi, Khil-Ohk Kang, Sang-Wook Kim, Dong-Duk Lee, Gyu-Han Yoon

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Proceedings Volume 4346, Optical Microlithography XIV; (2001) https://doi.org/10.1117/12.435634
Event: 26th Annual International Symposium on Microlithography, 2001, Santa Clara, CA, United States

Abstract

Leading chip makers are now trying to develop 130 nm technology node recently, using 0.70NA KrF lithography, whose k1 factor is 0.37. It is, however, accepted that it is a real challenge to apply low k1 process under 0.40 to mass- production. So, it is desirable to produce with higher k1 factor using such as 0.80NA KrF or 0.75NA ArF lithography. But, these advanced tools being not available yet, some chip makers who wish to produce 130 nm technology node device earlier have to choose low k1 process with 0.70NA KrF lithography. In mass-production, throughput and production yield are the most significant parameters that can define productivity and both parameters should be considered carefully when determining the size of a field. It is possible to organize several chips in a large field for better throughput, however it can cause degradation of CD uniformity, which can result in production yield drop, especially in low k1 process whose process window is not wide enough. On the contrary, using a small field may contribute to higher production yield, but at the expense of throughput. In this study, a model procedure to determine optimum field size by simulating the relative product yield and throughput is introduced for 130 nm technology node mass-production with low k1 process.

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Chan-Ha Park, Donggyu Yim, Seung-Hyuk Lee, Hyun-Jo Yang, Jae-Hak Choi, Yong-Chul Shin, Choi-Dong Kim, Jae-Sung Choi, Khil-Ohk Kang, Sang-Wook Kim, Dong-Duk Lee, and Gyu-Han Yoon "Optimum field-size strategy for DRAM mass production in low-k1 process", Proc. SPIE 4346, Optical Microlithography XIV, (14 September 2001); https://doi.org/10.1117/12.435634

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KEYWORDS

Semiconducting wafers

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Photomasks

Critical dimension metrology

Lithography

Chemical mechanical planarization

Electroluminescence

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