Paper
30 July 2002 Universal process modeling with VTRE for OPC
Author Affiliations +
Abstract
In previous work, Cobb and Zakhor (SPIE, 2726, pp.208-222, 1996) introduced the VTR (Variable Threshold Resist) model and demonstrated its accuracy for fitting empirical data for 365 nm illumination (SPIE, 3051, pp. 458-468, 1997). The original work showed how EPE can be modeled as a function of a peak local image intensity and the slope of the adjacent cutline. Since then, authors such as J. Randall, et al., (Microel. Engineering, 46, pp. 59-63, 1999) have analyzed the VTR model including other parameters such as dose. In the current approach, the original VTR has been enhanced to the VTR-Enhanced (or VTRE) in 1999, and VT-5 models in 2002, for production in OPC applications, which include other image intensity parameters. Here we present a comprehensive report on VT (Variable Threshold) process modeling. It has the demonstrated ability to accurately capture resist and etching responses, alone or in the combination with experimental VEB (Variable Etch Bias, SPIE, 4346, p. 98, 2001) model, for a wide range of process conditions used in the contemporary IC manufacturing. We analyzed 14 different semiconductor company processes experimental setups totaling 3000 CD measurements to prove this point. We considered 248, 193, and 157 nm annular and standard illumination sources for poly, metal, and active layers. We report an accuracy of VT family models under a wide range of conditions, show usage methodology, and introduce a novel method for calculating VTRE wafer predictions on a dense image intensity grid. We use multiple regression method to fit VT models and discuss methods for calculating regression coefficients. It is shown that models with too many eigenvectors exhibit a tendency to overfit CD curves. Sub-sample cross-validation and overfitting criteria are derived to avoid this problem. The section on test pattern and usage methodology describes practical issues needed for VT usage in OPC modeling. Particularly we discuss the effects of metrology errors on modeling. Also we introduce criteria for the important issue of model stability and propose refined test pattern structures designed to uniformly cover the VT parameter ranges. It is often required that the model has to 'hit' some CD measurements exactly. We introduce the 'bubble' technique to accomplish this. A 'bubble' constitutes an additional term in the VT functional form; it explains single CD measurement. We demonstrate how 'bubbles' help fit the pitch uniformity and iso-line linearity curves exactly. Lastly, the section on dense region calculation demonstrates how this TCAD-oriented technique can be used for tuning OPC algorithms. In its original form, VTR can easily be applied to sparse imaging at sample sites for OPC/ORC applications. It is useful to be able to calculate the VT wafer prediction for a fully dense grid of values, and plot the results like an aerial image contour plot.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yuri Granik, Nicolas B. Cobb, and Thuy Do "Universal process modeling with VTRE for OPC", Proc. SPIE 4691, Optical Microlithography XV, (30 July 2002); https://doi.org/10.1117/12.474587
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CITATIONS
Cited by 24 scholarly publications and 24 patents.
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KEYWORDS
Optical proximity correction

Data modeling

Critical dimension metrology

Semiconducting wafers

Performance modeling

Process modeling

Error analysis

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