Highly manufacturable capacitor-less 1T-DRAM concept

Pierre C. Fazan; Serguei Okhonin; Mikhail Nagoga; Jean-Michel Sallese

doi:10.1117/12.475684

12 July 2002 Highly manufacturable capacitor-less 1T-DRAM concept

Pierre C. Fazan, Serguei Okhonin, Mikhail Nagoga, Jean-Michel Sallese

Proceedings Volume 4692, Design, Process Integration, and Characterization for Microelectronics; (2002) https://doi.org/10.1117/12.475684
Event: Design, Process Integration, and Characterization for Microelectronics, 2002, Santa Clara, CA, United States

Abstract

We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.

Citation Download Citation

Pierre C. Fazan, Serguei Okhonin, Mikhail Nagoga, and Jean-Michel Sallese "Highly manufacturable capacitor-less 1T-DRAM concept", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); https://doi.org/10.1117/12.475684

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