Paper
26 June 2003 Image-blur tolerances for 65-nm and 45-nm node IC manufacturing
Author Affiliations +
Abstract
The deployment of 157nm lithography for manufacturing of integrated circuits is faced with many challenges. The 65 and 45nm ITRS nodes, in particular, require that the lithographic imaging technology be pursued to its theoretical limits with full use of the strongest resolution enhancement techniques. Stringent demands are therefore placed on the quality of the imaging optics to attain the optimal image fidelity for all critical IC device structures. Besides aberrations and light scatter in projection optics, image quality is also strongly influenced by the dynamics of the wafer and reticle stage. The tradeoffs involved in increasing scan speeds and exposure slit-widths, to achieve the ever-important productivity improvements as well as aberration, distortion, and pulse-energy averaging, must be carefully gauged against the image quality impacts of scan-induced errors. In this work, we present a simulation methodology, based on incoherent image superposition, for treatment of the general aerial image effects of transverse image-blur in two dimensions. Initial simulations and experimental results from state-of-the-art 193nm scanner exposures are discussed. The requirements for the transverse image stability during a step-and-scan exposure are defined in the context of 193nm and 157nm lithography, based on generalized image contrast and process window criteria. Furthermore, careful consideration of actual mask layout (post resolution enhancement and optical proximity correction) is necessary in order to understand the implications on CD control. Additionally, we discuss the contributors to transverse image blur in scan-and-repeat lithography, and show that the fading requirements for 65nm and 45nm node imaging notably differ from predicted exposure set-up and process contributions in manufacturing. The total fading budget, or tolerance, for the 65nm node is 15nm, and less than 10nm for the 45nm node given the present imaging strategy assumptions. This work concludes that image-blur contributors must be well controlled, and as such are enablers of 65nm and 45nm lithographic imaging.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ivan Lalovic, Armen Kroyan, Jongwook Kye, Hua-Yu Liu, and Harry J. Levinson "Image-blur tolerances for 65-nm and 45-nm node IC manufacturing", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); https://doi.org/10.1117/12.485510
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Cited by 3 scholarly publications.
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KEYWORDS
Critical dimension metrology

Semiconducting wafers

Image processing

Reticles

Lithography

Manufacturing

Nanoimprint lithography

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