New lifting folded pipelined discrete wavelet transform architecture

Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Vicente Herrero; Ricardo Colom

doi:10.1117/12.499049

21 April 2003 New lifting folded pipelined discrete wavelet transform architecture

Guillermo Paya, Marcos M. Peiro, J. Francisco Ballester, Vicente Herrero, Ricardo Colom

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.499049
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

The present work describes a new architecture for a CDF(2,2) wavelet base. The proposed architecture is based on the recursive pyramid algorithm (RPA) and the multirate folding technique to obtain better performance. The used of folding and retiming techniques improves the area and speed-rate. In order to obtain a maximally fast structure, we have modified the initial architecture scheduling getting internal pipelining delays to minimize the logic depth to one adder. Two different implementations using lifting scheme and polyphase decomposition are discussed. The lifting implementation requires approximately 52 % less hardware resources than the polyphase structure. Finally a comparative between our architecture and others folded architectures, which make all the computations into one filter bank, is presented. Our folded architecture reduces the number of registers and logic operators, increasing the frequency operation and minimizing the occupied area with the same throughput (one input / one output). Moreover, replicating delays block we can easily scale this architecture up. Our architecture performances an 87,5% hardware utilization.

Citation Download Citation

Guillermo Paya, Marcos M. Peiro, J. Francisco Ballester, Vicente Herrero, and Ricardo Colom "New lifting folded pipelined discrete wavelet transform architecture", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.499049

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