Bridging nanometer design-to-manufacturing gap: automated design rules correction and silicon verification

Linard N. Karklin; Micha Oren; Dragos Dudau; James D. Jordan

doi:10.1117/12.504251

28 August 2003 Bridging nanometer design-to-manufacturing gap: automated design rules correction and silicon verification

Linard N. Karklin, Micha Oren, Dragos Dudau, James D. Jordan

Author Affiliations +

Proceedings Volume 5130, Photomask and Next-Generation Lithography Mask Technology X; (2003) https://doi.org/10.1117/12.504251
Event: Photomask and Next Generation Lithography Mask Technology X, 2003, Yokohama, Japan

Abstract

Following Moore's Law semiconductor industry is going through a challenging transition from 180 nm to 130 nm manufacturing process geometries and rapidly approaching 90 nm geometries. The major challenges associated with the transition to nanometer design include: (1) Increasing design sizes and complexity (e.g. 300-400M transistors for FPGAs); (2) Increasing number of design rules (approaching 2000 for advanced 90 nm processes); (3) Increasing design cycle (4-9 months for ASICs); (4) Increasing design cost (advanced design flow cost $15M+). With the size and complexity of today's advanced ASICs and SoCs, the ability of designers to efficiently fix DRC errors is becoming a critical challenge impacting productivity and time-to-market. Designers need new EDA tools to process designs of very high complexity in shorter time. New tools should bridge design and process worlds by transparently providing designers with more detailed process (lithography) information. In this paper the authors will describe a method for manufacturing verification of automated design rule fixes. Many types of design rule violation are detected, automatically fixed, and verified by lithography simulation.

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Linard N. Karklin, Micha Oren, Dragos Dudau, and James D. Jordan "Bridging nanometer design-to-manufacturing gap: automated design rules correction and silicon verification", Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); https://doi.org/10.1117/12.504251

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