Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

Soo-Han Choi; Tae-Hoon Park; Eunsung Kim; Hyoung-Joo Youn; Dae-Youp Lee; Yong-Chan Ban; A-Young Je; Dong-Hyun Kim; Ji-Suk Hong; Yoo-Hyon Kim; Moon-Hyun Yoo; Jeong-Taek Kong

doi:10.1117/12.600249

12 May 2005 Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

Soo-Han Choi, Tae-Hoon Park, Eunsung Kim, Hyoung-Joo Youn, Dae-Youp Lee, Yong-Chan Ban, A-Young Je, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Author Affiliations +

Proceedings Volume 5754, Optical Microlithography XVIII; (2005) https://doi.org/10.1117/12.600249
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL) [1] is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.

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Soo-Han Choi, Tae-Hoon Park, Eunsung Kim, Hyoung-Joo Youn, Dae-Youp Lee, Yong-Chan Ban, A-Young Je, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, and Jeong-Taek Kong "Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005); https://doi.org/10.1117/12.600249

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