Impact of leakage on high-performance designs

Aniket M. Saha; Earl E. Swartzlander Jr.

doi:10.1117/12.617568

16 September 2005 Impact of leakage on high performance designs

Aniket M. Saha, Earl E. Swartzlander Jr.

Proceedings Volume 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV; 59100P (2005) https://doi.org/10.1117/12.617568
Event: Optics and Photonics 2005, 2005, San Diego, California, United States

Abstract

With aggressive technology scaling there has been a rapid increase in leakage currents in modern CMOS processes. Leakage is mainly composed of sub-threshold and gate leakage. Leakage has been exponentially increasing with the scaling of threshold voltage and gate oxide thickness. This has resulted in power consumption being drastically affected. With the explosive increase in usage of embedded multimedia processors, high performance circuits need to be ultra low power in the standby mode while having a moderate power budget during runtime. One of the most power consuming high performance macros of an embedded processor is the floating point unit. In this paper we look into various macros of a floating point unit designed using a dynamic power optimized logic style called Limited Switch Dynamic Logic and circuit solutions for reducing the impact of leakage on these macros. The results are obtained for CMOS technology nodes of 90nm and 65nm.

Citation Download Citation

Aniket M. Saha and Earl E. Swartzlander Jr. "Impact of leakage on high performance designs", Proc. SPIE 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV, 59100P (16 September 2005); https://doi.org/10.1117/12.617568

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