Inverse lithography technology at chip scale

Benjamin Lin; Ming Feng Shieh; Jie-wei Sun; Jonathan Ho; Yan Wang; Xin Wu; Wolfgang Leitermann; Orson Lin; Jason Lin; Yong Liu; Linyong Pang

doi:10.1117/12.656827

21 March 2006 Inverse lithography technology at chip scale

Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Author Affiliations +

Proceedings Volume 6154, Optical Microlithography XIX; 615414 (2006) https://doi.org/10.1117/12.656827
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We discuss some specifics of ILT at chip-scale. We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing results from ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.

Citation Download Citation

Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Orson Lin, Jason Lin, Yong Liu, and Linyong Pang "Inverse lithography technology at chip scale", Proc. SPIE 6154, Optical Microlithography XIX, 615414 (21 March 2006); https://doi.org/10.1117/12.656827

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