Performance estimates of radar STAP processing on the IBM/Sony/Toshiba cell processor

Luke Cico; Jon Greene

doi:10.1117/12.666216

8 May 2006 Performance estimates of radar STAP processing on the IBM/Sony/Toshiba cell processor

Luke Cico, Jon Greene

Proceedings Volume 6210, Radar Sensor Technology X; 62100D (2006) https://doi.org/10.1117/12.666216
Event: Defense and Security Symposium, 2006, Orlando (Kissimmee), Florida, United States

Abstract

Advances in commercial off-the-shelf (COTS) embedded computing technologies have yielded impressive gains in computational throughput over the past 5-10 years. Adaptive sensor array systems utilizing real-time teraflop class machines are in wide deployment today. Gains in processor density have generally been achieved by steady improvements in semiconductor optical lithographic processes along with less frequent innovations in processor chip architectures. It is likely that the real-time embedded community is entering an era where processor architectural innovations will be bearing most of the burden for producing processing density gains as lithographic processes approach fundamental physical limitations. More and more 'systems on a chip' are emerging to address these trends. An exciting example of this technology trend is IBM's new Cell Broadband Engine (CBE) architecture which offers massive SIMD compute power on multiple computational units interconnected via a high bandwidth internal fabric. This paper explores the application of a computationally intensive adaptive nulling problem on the CBE architecture.

Citation Download Citation

Luke Cico and Jon Greene "Performance estimates of radar STAP processing on the IBM/Sony/Toshiba cell processor", Proc. SPIE 6210, Radar Sensor Technology X, 62100D (8 May 2006); https://doi.org/10.1117/12.666216

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