Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations

Kevin Lucas; Chris Cork; Jonathan Cobb; Brian Ward; Martin Drapeau; Charlie Zhang; John Allgair; Mike Kling; Mike Rieger

doi:10.1117/12.715166

27 March 2007 Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations

Kevin Lucas, Chris Cork, Jonathan Cobb, Brian Ward, Martin Drapeau, Charlie Zhang, John Allgair, Mike Kling, Mike Rieger

Author Affiliations +

Proceedings Volume 6520, Optical Microlithography XX; 65200N (2007) https://doi.org/10.1117/12.715166
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed. In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

Citation Download Citation

Kevin Lucas, Chris Cork, Jonathan Cobb, Brian Ward, Martin Drapeau, Charlie Zhang, John Allgair, Mike Kling, and Mike Rieger "Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations", Proc. SPIE 6520, Optical Microlithography XX, 65200N (27 March 2007); https://doi.org/10.1117/12.715166

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