Development of multi-layer process materials for hyper-NA lithography process

Yasushi Sakaida; Makoto Nakajima; Tetsuya Shinjo; Keisuke Hashimoto

doi:10.1117/12.804688

4 December 2008 Development of multi-layer process materials for hyper-NA lithography process

Yasushi Sakaida, Makoto Nakajima, Tetsuya Shinjo, Keisuke Hashimoto

Proceedings Volume 7140, Lithography Asia 2008; 71403Z (2008) https://doi.org/10.1117/12.804688
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan

Abstract

In order to achieve miniaturization of the device, and still following device design rules, the photo-resist film thickness has decreased. The thinner photo-resist thickness will improve the resolution limit and prevent the pattern collapse issue. In order to solve these problems a multilayer process is used that has several advantages over previous process designs: reflectivity control in hyper-NA lithography process, decreasing LWR, and the viewpoint of lithographic process margin. The multilayer process consists of three layers: layer one is patterned photo-resist, the second layer is Si-ARC (Si contented Anti Reflective Coatings), and the third layer is SOC (Spin on Carbon) also known as underlayer. There are two processes to deposit Si-ARC and SOC, the first is by spin coating with either a track or spin coater, the second is with a Chemical Vapor Deposition (CVD). From a cost of ownership standpoint the spin on process is better. In the development of spin on Si-ARC and SOC materials it is important to consider the resist profile and the shelf life stabilities. Another important attribute to consider is the etching characteristics of the material. For the Si-ARC the main attribute when determining etch rate is the Si content and for the SOC material the main attribute is the C content in the material. One problem with the spin on multilayer process is resist profile and this paper will examine this problem along with the characteristics of developed material is described.

Citation Download Citation

Yasushi Sakaida, Makoto Nakajima, Tetsuya Shinjo, and Keisuke Hashimoto "Development of multi-layer process materials for hyper-NA lithography process", Proc. SPIE 7140, Lithography Asia 2008, 71403Z (4 December 2008); https://doi.org/10.1117/12.804688

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KEYWORDS

System on a chip

Silicon

Etching

Lithography

Reflectivity

Semiconducting wafers

Materials processing

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