The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high
resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop
solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that
the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a
manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can
provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This
strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the
development of the mask form factor, imprint replication tools and processes specifically for semiconductor
applications.
The requirements needed for semiconductors dictate the need for a well defined form factor for both master and
replica masks which is also compatible with the existing mask infrastructure established for the 6025 semi standard, 6"
x 6" x 0.25" photomasks. Complying with this standard provides the necessary tooling needed for mask fabrication
processes, cleaning, metrology, and inspection. The replica form factor has additional features specific to imprinting
such as a pre-patterned mesa. A PerfectaTM MR5000 mask replication tool has been developed specifically to pattern
replica masks from an e-beam written master. The system specifications include a throughput of four replicas per hour
with an added image placement component of 5nm, 3sigma and a critical dimension uniformity error of less than 1nm,
3sigma. A new process has been developed to fabricate replicas with high contrast alignment marks so that designs for
imprint can fit within current device layouts and maximize the usable printed area on the wafer. Initial performance
results of this marks are comparable to the baseline fused silica align marks.
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