DSPACE hardware architecture for on-board real-time image/video processing in European space missions

Sergio Saponara; Massimiliano Donati; Luca Fanucci; Maximilian Odendahl; Reiner Leupers; Walter Errico

doi:10.1117/12.2002096

19 February 2013 DSPACE hardware architecture for on-board real-time image/video processing in European space missions

Sergio Saponara, Massimiliano Donati, Luca Fanucci, Maximilian Odendahl, Reiner Leupers, Walter Errico

Proceedings Volume 8656, Real-Time Image and Video Processing 2013; 86560D (2013) https://doi.org/10.1117/12.2002096
Event: IS&T/SPIE Electronic Imaging, 2013, Burlingame, California, United States

Abstract

The on-board data processing is a vital task for any satellite and spacecraft due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. In the last years the amount of sensing data collected by scientific and commercial space missions has increased significantly, while the available downlink bandwidth is comparatively stable. The increasing demand of on-board real-time processing capabilities represents one of the critical issues in forthcoming European missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications. The only available space-qualified Digital Signal Processor (DSP) free of International Traffic in Arms Regulations (ITAR) restrictions faces inadequate performance, thus the development of a next generation European DSP is well known to the space community. The DSPACE space-qualified DSP architecture fills the gap between the computational requirements and the available devices. It leverages a pipelined and massively parallel core based on the Very Long Instruction Word (VLIW) paradigm, with 64 registers and 8 operational units, along with cache memories, memory controllers and SpaceWire interfaces. Both the synthesizable VHDL and the software development tools are generated from the LISA high-level model. A Xilinx-XC7K325T FPGA is chosen to realize a compact PCI demonstrator board. Finally first synthesis results on CMOS standard cell technology (ASIC 180 nm) show an area of around 380 kgates and a peak performance of 1000 MIPS and 750 MFLOPS at 125MHz.

Citation Download Citation

Sergio Saponara, Massimiliano Donati, Luca Fanucci, Maximilian Odendahl, Reiner Leupers, and Walter Errico "DSPACE hardware architecture for on-board real-time image/video processing in European space missions ", Proc. SPIE 8656, Real-Time Image and Video Processing 2013, 86560D (19 February 2013); https://doi.org/10.1117/12.2002096

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