Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification

Yuelin Du; Hua Song; James Shiely; Martin D. F. Wong

doi:10.1117/12.2011029

29 March 2013 Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification

Yuelin Du, Hua Song, James Shiely, Martin D. F. Wong

Proceedings Volume 8684, Design for Manufacturability through Design-Process Integration VII; 86840D (2013) https://doi.org/10.1117/12.2011029
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.

Citation Download Citation

Yuelin Du, Hua Song, James Shiely, and Martin D. F. Wong "Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification", Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840D (29 March 2013); https://doi.org/10.1117/12.2011029

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