Paper
9 September 2013 Under-layer effects for block levels: are they under control?
Dongbing Shao, Bidan Zhang, Shayak Banerjee, Hong Kry, Anuja De Silva, Ranee Kwong, Kisup Chung, Yea-Sen Lin, Alan Leslie
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Abstract
Challenges in block levels due to the dilemma of cost control and under-layer effects have been addressed in several papers already, and different approaches to solve the issue have been addressed. Among the known approaches, developable BARC and under-layer aware modeling are the most promising. However, in this paper we will discuss and explain the limitation inefficiency of both methods. In addition, as more block levels are employing etching step, the under-layer dependent etch behavior that we see in some of the block levels is also discussed. All these place great challenges for block level process development. We discuss here possible solutions/improvements including: developable BARC (dBARC) thickness optimization for specific under layers; Simplified model based corrections for lith and etch. This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dongbing Shao, Bidan Zhang, Shayak Banerjee, Hong Kry, Anuja De Silva, Ranee Kwong, Kisup Chung, Yea-Sen Lin, and Alan Leslie "Under-layer effects for block levels: are they under control?", Proc. SPIE 8880, Photomask Technology 2013, 88802L (9 September 2013); https://doi.org/10.1117/12.2029356
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KEYWORDS
Critical dimension metrology

Silicon

Etching

Semiconducting wafers

Optical proximity correction

Near field optics

Reflectivity

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