Novel processor architecture for onboard infrared sensors

Hiroki Hihara; Akira Iwasaki; Nobuo Tamagawa; Mitsunobu Kuribayashi; Masanori Hashimoto; Yukio Mitsuyama; Hiroyuki Ochi; Hidetoshi Onodera; Hiroyuki Kanbara; Kazutoshi Wakabayashi; Munehiro Tada

doi:10.1117/12.2237433

14 September 2016 Novel processor architecture for onboard infrared sensors

Hiroki Hihara, Akira Iwasaki, Nobuo Tamagawa, Mitsunobu Kuribayashi, Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Munehiro Tada

Author Affiliations +

Proceedings Volume 9973, Infrared Remote Sensing and Instrumentation XXIV; 99730S (2016) https://doi.org/10.1117/12.2237433
Event: SPIE Optical Engineering + Applications, 2016, San Diego, California, United States

Abstract

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

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Hiroki Hihara, Akira Iwasaki, Nobuo Tamagawa, Mitsunobu Kuribayashi, Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, and Munehiro Tada "Novel processor architecture for onboard infrared sensors", Proc. SPIE 9973, Infrared Remote Sensing and Instrumentation XXIV, 99730S (14 September 2016); https://doi.org/10.1117/12.2237433

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