Photonics ASICs: a promising approach toward high throughput, short latency, and parallelized computing hardware

Hamed Dalir

doi:10.1117/12.2650978

17 March 2023 Photonics ASICs: a promising approach toward high throughput, short latency, and parallelized computing hardware

Hamed Dalir

Author Affiliations +

Proceedings Volume PC12438, AI and Optical Data Sciences IV; PC124380A (2023) https://doi.org/10.1117/12.2650978
Event: SPIE OPTO, 2023, San Francisco, California, United States

Abstract

Data growth and AI demand low-latency hardware. ML is 90% convolutions (conv). (N-K), where N is input and kernel matrix size (assuming squared matrices). Classification ML kernel-weight changes are infrequent. Photonic ASICs benefit from compute-in-memory. Photonic memory accesses in 0.3ns and uses 100fJ/access, 100x less than SRAM. PCM photonic memory needed photon production and detection. C-band PIC detectors require 50nW above 30GHz. Assuming 1% laser wall-plug efficiency and 2dB per coupler, PCM-written P-RAM memory READ energy is 1fJ/access for OOK signal at 30GHz data rates, or 10fJ/access for greater bit resolution. Photonic connections 100x faster than SRAM. Off-chip learning kernels can execute conv-underlying MAC operations on electro-optic PICs. Specifically, utilizing fiber optical-based discrete components (non-PIC based) and PIC-based demonstrations show the possibility for efficient photonic MAC and hence conv. acceleration.

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Hamed Dalir "Photonics ASICs: a promising approach toward high throughput, short latency, and parallelized computing hardware", Proc. SPIE PC12438, AI and Optical Data Sciences IV, PC124380A (17 March 2023); https://doi.org/10.1117/12.2650978

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KEYWORDS

Photonics

Photonic integrated circuits

Energy efficiency

Fiber optics

Machine learning

Matrices

Photodetectors

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