622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit

Chul-Soo Park; Chung-Ghiu Lee; Chang-Soo Park

doi:10.1117/1.2012328

1 August 2005 622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit

Chul-Soo Park, Chung-Ghiu Lee, Chang-Soo Park

Author Affiliations +

Optical Engineering, Vol. 44, Issue 8, 085004 (August 2005). https://doi.org/10.1117/1.2012328

Abstract

A clock and data recovery circuit using the clock jitter reduction technique is proposed for a 622-Mbit/s burst-mode data stream. The clock jitter reduction is achieved by controlling the clock duty cycle with the phase information of the recovered clock. The proposed clock recovery circuit, based on the gated oscillator, recovers a low-jitter output clock with up to 4090 consecutive zeros.

©(2005) Society of Photo-Optical Instrumentation Engineers (SPIE)

Citation Download Citation

Chul-Soo Park, Chung-Ghiu Lee, and Chang-Soo Park "622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit," Optical Engineering 44(8), 085004 (1 August 2005). https://doi.org/10.1117/1.2012328

Published: 1 August 2005

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