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The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device
technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second
generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical
part of technology enablement as scaling has become more challenging and the industry pushes the limits
of EUV lithography. The working partnership between the design teams and the process development
teams typically involves an iterative approach to evaluate the manufacturability of proposed designs,
subsequent modifications to those designs and finally a design manual for the technology. While this
approach has served the industry well for many generations, the challenges at the Beyond 7nm node require
a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout
optimization where we remove the iterative component of DTCO and replace it with an optimization that
achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects.
Solved together, this “design intent” approach can more quickly achieve superior lithographic results while
still meeting the original device’s functional specifications.
Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using
design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either
supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic
behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall
optimization. We will show the benefit of the “design intent approach” on both bidirectional and
unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO
approach. Thus demonstrating the benefit of allowing the design to float within the specified range.
Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on
some minimal set of functional requirements and process constraints.
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