Presentation + Paper
28 April 2023 Full chip inverse lithography technology mask synthesis for advanced memory manufacturing
Author Affiliations +
Abstract
In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jennefir Digaum, Gary Chiang, Lin Wang, Kyle Braam, Dave Gerold, Yongdong Wang, and Thuc Dam "Full chip inverse lithography technology mask synthesis for advanced memory manufacturing", Proc. SPIE 12495, DTCO and Computational Patterning II, 1249503 (28 April 2023); https://doi.org/10.1117/12.2657538
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KEYWORDS
Design and modelling

Optical proximity correction

Lithography

Semiconducting wafers

Manufacturing

Visualization

Reticles

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