Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Axel Nackaerts; Staf Verhaegen; Mircea Dusa; Hans Kattouw; Frank van Bilsen; Serge Biesemans; Geert Vandenberghe

doi:10.1117/12.713385

21 March 2007 Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Axel Nackaerts, Staf Verhaegen, Mircea Dusa, Hans Kattouw, Frank van Bilsen, Serge Biesemans, Geert Vandenberghe

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65210N (2007) https://doi.org/10.1117/12.713385
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

In this paper the impact of overlay and CD uniformity specifications on device and SRAM cell functional and parametric yield are analyzed. The variation of channel strain due to partial etching of the stress layer is determined, and we find that including this effect in the device parametric yield leads to severe CDU and overlay requirements. The method is applied to SRAM cells and memories, and it is shown that only the co-optimization of SRAM cell layout, CDU and overlay can increase the number of good dies per wafer.

Citation Download Citation

Axel Nackaerts, Staf Verhaegen, Mircea Dusa, Hans Kattouw, Frank van Bilsen, Serge Biesemans, and Geert Vandenberghe "Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210N (21 March 2007); https://doi.org/10.1117/12.713385

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