2.1

Phase shifter concept

While higher doping levels generally result in a higher modulation efficiency, they also translate into higher free carrier absorption. The product of the free carrier absorption losses α with the drive voltage, quantified by the associated figure of merit α·V_πL, scales unfavorably at higher doping levels. For example, increasing the n- and p-doping levels by a factor 5 in the phase shifter shown in Fig. 1(a), from n, p=5e17 cm^-3 to n, p=2.5e18 cm^-3 (both reasonable doping levels [8, 9]) results in the effective index change Δn_eff increasing from 8e-5 to 16e-5 for a 2 V_pp reverse voltage swing and optical losses increasing from 1.2 dB/mm to 7.1 dB/mm (assuming the width of the intrinsic region to be 20 nm, the height of the waveguide to be 220 nm and the etch depth to be 120 nm). The loss increases by a factor 6 while Δn_eff is only doubled. The two quantities scale differently since the variation of the depletion region width (ΔW_Dep) versus applied reverse voltage decreases at higher doping levels, resulting in a reduced overlap with the region in which the free carrier concentration and thus the refractive index is modulated, while waveguide losses scale directly with the dopant concentration assuming most of the waveguide to be doped.

Fig. 1:

schematic of different depletion-type phase shifter configurations. (a) Horizontal junction (b) horizontal junction with highly doped regions in the vicinity of the junction (c) vertical junction with narrow highly doped regions in the vicinity of the junction and top contacting with amorphous silicon, and (d) proposed phase shifter.

This suggests that the highly doped region should be present only in the vicinity of the depletion region and not in the whole phase shifter waveguide cross section. The structure in Fig. 1(b) illustrates this concept. As an example, if the doping concentrations are set to n⁺,p⁺=2.5e18 cm^-3 within 15 nm of the 20 nm wide intrinsic region and the rest of the waveguide is doped with n^-,p^-=5e17 cm^-3 simulations show an optical loss of 1.7 dB/mm (only slightly higher than for the low doped version of Fig. 1(a)) and a Δn_eff of 16e-5 (same as for the highly doped version of Fig. 1(a)), resulting in a significant improvement. Since this structure is impractical to fabricate, alternative implementations have to be explored. Figure 1(c) shows a cross section of a modulator translating the same concept in a vertical junction. This structure can be fabricated e.g. by means of epitaxial growth of in-situ doped silicon, allowing sufficient control over the doping profile as experimentally shown in section 2.3. The thickness of each layer can be controlled in a range down to a few nanometers, since epitaxial growth of silicon is a relatively slow process. However, the structure shown in Fig. 1(c) requires a planarization process and deposition of poly- or amorphous silicon on top of the phase shifter and the surrounding oxide cladding in order to define the top contact. Polycrystalline and amorphous silicon are suboptimum in terms of optical losses per material conductivity [6,7]. The structure shown in Fig. 1(d) on the other hand does not require an additional poly- or amorphous silicon layer, since the thin p⁺ and n⁺ layers defining the pin diode can also be used for electrical contacting. Most of the volume of the phase shifter is left undoped. Therefore, higher implantation levels up to 1e19 cm^-3 can be implemented and high modulation efficiency is achievable without excessive free carrier absorption losses.

2.2

Fabrication process

The vertical junction depicted in Fig. 1(d) can be fabricated by means of epitaxial growth of in-situ doped silicon stacks. In-situ doping during chemical vapor deposition (CVD) of epitaxial silicon layers makes it possible to fabricate silicon stacks with thin highly doped layers with high dopant activation. It does not add ion-implantation mediated damage to the crystalline structure of the silicon, which can result in enhanced dopant diffusion, additional optical losses and lead to complications during epitaxial overgrowth. Compared to ion-implantation, in-situ doping gives much more control over the doped layer thicknesses, particularly for Boron for which the formation of highly doped shallow wells with ion-implantation technology is particularly difficult. Moreover, in-situ doped silicon does not require dopant activation and thus the thermal exposure after deposition of in-situ doped layers is limited to the subsequent silicon deposition (at 800°C). The anticipated process flow is shown in Fig. 2, starting with silicon-on-insulator (SOI) wafers with a 2 μm buried oxide and a 220 nm thick silicon device layer. After thinning down the device layer to 50 nm by thermal oxidation followed by wet etching in a buffered HF solution, the crystalline silicon is homogenously deposited by CVD using disilane as a precursor at a temperature of 800°C with a deposition rate of about 5 nm/min. Dopants are added by introducing diborane (B₂H₆) and phosphine (PH₃) gases to the chamber, respectively for p- and n-doping. The total thickness of the deposited silicon stack is chosen to be 290 nm. Waveguides are defined by etching the top silicon asymmetrically by respectively 200 nm and 150 nm on the p- and n-contact side. In order to increase the device bandwidth and minimize the power consumption, it is desirable to restrict the capacitor to the waveguide region. This is achieved by the deeper etch on the p-contact side. Unfortunately, in this process flow the capacitor is extended up to the n⁺⁺ well on the n-contact side, resulting in a suboptimum capacitance.

Fig 2.

Illustration of the fabrication flow (wafer thinning, epitaxial growth, waveguide definition, implantation of contact wells followed by aluminum sputtering and a lift-off process for contact definition).

Once the waveguide is formed, p⁺⁺ and n⁺⁺ wells are formed on either side of the waveguide by ion implantation with concentrations of ~1e20 cm^-3 (sufficient to overcompensate overlapping p⁺ doping in the case of the n⁺⁺ well) to provide an ohmic contact between the silicon and the metal. In order to obtain acceptable contact well mediated excess waveguide losses while maintaining an adequate RC bandwidth, the p- and n-wells are defined 600 nm and 800 nm from the waveguide edge, respectively. Subsequently, aluminum contacts are deposited by means of sputtering with a thickness of 2 μm and patterned with a lift-off process. Fig. 2(6) shows the final cross section of the modulator.

2.3

Experimental validation of the concept

To verify the accuracy and feature sizes that can be reached for the doping distribution, we experimentally validated the epitaxial growth process, with characterization results of a process calibration run shown in Fig. 3. Rutherford Backscattering Spectrometry (RBS) measurements were performed in both random and channeling mode utilizing 1.4 MeV He⁺ ions at a scattering angle of 170°. Due to the low atomic concentration of the dopants, only silicon atoms contribute to the random spectrum in Fig. 3(a). The channeling spectrum of the epitaxially grown silicon stack displays no difference to that of a bulk silicon wafer, showing the grown layers to have a high crystalline quality. The minimum channeling yield χ_min, defined as the ratio between channeling and random spectra for energies below the surface peak, amounts to about 4 %, indicating an excellent substitutionality of the silicon atoms. To determine the electrically active carrier concentrations in the grown layer, electrochemical capacitance-voltage (ECV) measurements were performed, as shown in Fig. 3(b). The measured thicknesses and doping profiles match the targeted geometry (inset of Fig. 3(a)) and demonstrate the high level of control over layer thicknesses and dopant concentrations.

Fig. 3.

(a) Rutherford backscattering spectrometry (RBS) measurements performed on the grown epitaxial stack. The inset shows the targeted geometry. (b) Doping profile of the silicon stack from Electrochemical Capacitance-Voltage (ECV) measurements.

3.1

Phase shifter design

The targeted doping levels of the p- and n-doped regions inside the rib waveguide are the result of a tradeoff between total optical loss, modulation efficiency and electro-optic cutoff frequency. Figures 4(a) and 4(c) show the calculated Δn_eff and optical loss for a 2 V_pp voltage swing applied to the phase shifter (0 V to 2 V reverse bias) versus donor and acceptor concentrations N_d and N_a. The thickness of the intrinsic layer is h_int=50 nm, the thicknesses of p- and n-doped layers are respectively 30 nm and 20 nm. The modulator length required to achieve π/2 phase shift (assuming a dual drive Mach-Zehnder Modulator (MZM) operated in push pull configuration) is then evaluated as L_π/2 = λ/(4Δn_eff) (Fig. 4(b)) and the resulting insertion losses calculated (Fig. 4(d)). The calculated 3 dBe intrinsic cutoff frequency of the phase shifter (f_c=1/2πRC) also improves at higher doping levels (Fig. 4(e)), since the capacitance asymptotically converges to that of a parallel plate capacitor with a spacing h_int between the electrodes, while the series resistance continues to drop at high doping levels.

Fig. 4.

(a) Effective index change between 0 V and 2 V reverse bias, (b) L_π/2 derived from (a), (c) optical loss per unit length, (d) total loss for a phase shifter reaching π/2 phase shift, (e) intrinsic cutoff frequency 1/2πRC, and (e) the FOM Δn_eff²·f_c/(αC_L).

A dual drive lumped element MZM with a drive voltage chosen to achieve full extinction and a length sized to reach 1 dB of waveguide losses has a power consumption given by C_L·V_πL²·α/8 [10], where C_L is the capacitance per unit length and α is in units of dB/length. We introduce the figure of merit FOM = Δn_eff²·f_c/(αC_L) proportional to the product of the inverse of the aforementioned power consumption with the intrinsic phase shifter bandwidth f_c. For the layer thicknesses described above, N_d=4e18 cm^-3 and N_a=8e18 cm^-3 maximize the figure of merit (Fig 4(f)).

This high doping levels result in a phase shifter with a relatively high capacitance of 1.62 nF/m and a low series resistance of 2.29 mΩ·m (both at 0 V), which results in a 42 GHz intrinsic bandwidth. The free carrier absorption losses are 4.5 dB/mm (also at 0 V). Applying a 2 V reverse bias to the phase shifter results in an effective index change of 2.7e-4, which requires a length of 1.4 mm to achieve a π/2-phase shift (V_πL=0.56 V·cm).

The cross section of the optimized silicon stack is shown in Fig. 5(a). We have also fabricated this layer stack with the process described in section 2.2. RBS measurements (Fig. 5(b)) confirm very high quality deposited silicon layers. The actual spatial carrier distribution was determined by an ECV measurement (Fig. 5(c)), which is in good agreement with the targeted structure. The tail of the n-dopants reaching inside the nominally intrinsic top silicon capping layer can be due to residual dopants inside the chamber and phosphorus segregation at the surface, since we did not interrupt the growth process for gettering the Phosphorous out of the chamber.

Fig. 5.

(a) Cross section of the targeted silicon stack, (b) RBS measurements and (c) doping profile of the stack as determined by ECV measurements.

In the next section, the layout and the simulated performance of a lumped element and a travelling wave modulator relying on the proposed phase shifter are reported.

3.2

Lumped element modulator

For a lumped element modulator (i.e., a short modulator relative to the RF wavelength in the structure, here with a length on the order of 1/10^th of the RF wavelength) the cutoff frequency of the device will be only limited by the RC time constant. Therefore, similar scaling of the linear capacitance C_L and the inverse linear diode series resistance 1/R_L will not affect the intrinsic bandwidth. On the other hand, a higher capacitance results in higher modulation efficiency. Moreover, the short device length makes it less sensitive to waveguide losses. Thus, lumped element modulator designs naturally gravitate towards high doping levels, a high capacitance and a low resistance. In that design space, the output impedance of the driver Z_dri plays a crucial role since the series resistance of the modulator is small and Z_dri plays a substantial role in the total series resistance. For instance, for the MZM shown in Fig. 6(a) which is 250 μm long, the total series resistance of one modulator arm is 9.2 Ω. Thus, a driver output impedance of Z_dri=10 Ω (Fig 6(b), blue curve), halves the intrinsic analog bandwidth. Reducing the driver impedance to a low but still realistic value Z_dri=4 Ω results in a bandwidth of 35 GHz at 2 V bias. The performance metrics of the device are summarized in table 1.

Fig. 6.

(a) Layout of the 250 μm lumped element MZM. The red and blue layers respectively represent p- and n-doped wells, the green layer represents metal electrodes. (b) Electro-optic S₂₁ of the lumped element MZM for two driver output impedances.

Table 1.

Performance metrics of the travelling-wave and the lumped element modulators using the proposed phase shifter.

3.3

Travelling wave modulator

In order to further reduce the required drive voltage, longer phase shifters are required. Figure 7 shows the layout of a travelling wave modulator in which the length of the waveguide is 1.4 mm. To achieve a high cutoff frequency, phase matching between the group velocity of the optical mode and the RF signal must be verified. To slow down the optical wave and obtain phase matching, we have increased the optical path length by meandering the waveguide. Metal extensions contact the metal lines to the waveguide, reducing the series resistance of the loaded transmission line (and thus reducing transmission line losses and increasing the electro-optic bandwidth) without increasing the fringe capacitance between the metal lines or significantly changing the RF index [11-12]. As in Fig. 6, the red and blue layers respectively represent the p- and n-doped wells. The high-speed performance of the device is calculated and the phase matching verified by means of the commercial finite element method solver HFSS from Ansys. The simulation results predict a cutoff frequency of 21 GHz mainly limited by RF losses in the transmission line. Since achieving a characteristic impedance of 50 Ω is very challenging due to the high capacitive load applied to the transmission line [12], the travelling wave modulator is designed for a 25 Ω system, which is also beneficial in terms of RF losses at the cost of increased power consumption [11-12].

Fig. 7.

Layout of the travelling wave modulator.