KEYWORDS: Resistance, Transistors, Manufacturing, Crystals, Diodes, System on a chip, Tolerancing, Very large scale integration, Power supplies, Switches
As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.
The stability of TiN which is the preferred bottom electrode contact (BEC) of phase change memory (PCM) due to its low thermal conductivity and suitable electrical conductivity, is very essential to the reliability of PCM devices. In this work, in order to investigate the effect of high aspect ratio process (HARP) SiO2 on the performance of TiN, both TiN/SiO2, TiN/SiN thin films and TiN BEC device structures are analyzed. By combining transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS), we found that the TiN would be oxidized after the deposition of HARP SiO2 and there exist a thin (~4 nm) oxidation interfacial layer between TiN and SiO2. Electrical measurements were performed on the 1R PCM test-key die with 7 nm and 10 nm BEC-only cells. The statistical initial resistances of BEC have wide distribution and it is confirmed that the non-uniform oxidation of TiN BEC affects the astringency of the resistance of TiN BEC. The experimental results help to optimize the process of TiN BEC, and SiN is recommended as a better choice as the linear layer.
In this work, we discuss about the formation of recessed hole in the manufacturing process of phase change memory (PCM). Three recessed holes with different slope angle and depth were obtained by changing the NF3/O2 gas mixing ratio. The recessed holes upon bottom electrode contact (BEC) were achieved by etch back process after the formation of BEC. The etching process takes advantage of the etch rate of TiN which is faster than that of SiN. With increasing content of O2 gas, the decrease in the etch rate of SiN was larger than that of TiN, and this increases the selectivity of TiN to SiN. Oxidation layer can be found upon the SiN layer in the energy dispersive X-ray (EDX) elemental mapping profile after the recessed etching step. It is the existence of oxidation layer that suppressed the etching of SiN.
A three-dimensional finite element model for Phase-Change Random Access Memory (PCRAM) is established to simulate thermal and electrical distribution during RESET operation. The establishment of the model is highly in accordance with the manufacture of PCRAM cell in the 40nm process and the model is applied to simulate the RESET behaviors of 35 nm diameter of titanium nitride (TiN) bottom electrode in the conventional mushroom structure (MS). By the simulations of thermal and electrical distribution, the highest temperature is observed in TiN bottom electrode contactor and meanwhile the voltage of the TiN bottom electrode accounts for as high as 65 percent of the total voltage. It induces high RESET current which suggests that the thermoelectric conductivity of MS is crucial in improving the heating efficiency in RESET process. Simulation results of RESET current and high resistance distribution during RESET operation are close to the data from the actual measurement. However those two values of low resistance are slightly different, probably due to the interface resistance between Ge2Sb2Te5 (GST) and other materials and the resistance caused by microstructural defects. This work reveals the importance of the thermoelectrical properties of materials in PCRAM cells and improves the quality of PCRAM simulations in industrial application.
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